CS698Y: Modern Memory Systems Lecture-2 (Brushing-up Computer Architecture) Biswabandan Panda
|
|
|
- Kristin Morton
- 6 years ago
- Views:
Transcription
1 CS698Y: Modern Memory Systems Lecture-2 (Brushing-up Computer Architecture) Biswabandan Panda
2 Why you want to enroll for CS698Y? YES Assignment-0 (Highlights) A link to your web-page/linkedin that has your smiling face None Type the following: "I promise, I will." YES Any other comments/suggestions that you have for me or for CS698Y? Please give good grades What you want to do after your B.Tech/M.Tech/M.S./Ph.D.? Teaching (that too poor students of India) Modern Memory Systems Biswabandan Panda, CSE@IITK 2
3 Logistics Contact: KD 203, Office Hours: Tues/Fri: 12 noon, by appointment No participation in Piazza yet (oh wait, Partha had it in the last minute). There is chance of losing 10 points We have a T.A. now: Saurabh (Pursuing Ph.D. in Android security) What about a 5min break at 11.15Hrs or so? Stop me if you feel like not listening to me Modern Memory Systems Biswabandan Panda, CSE@IITK 3
4 Shall I Freeze it? Option-I: 30 = (3 10) = 3 programming assignments 40 = (2 20) = Quiz 1.0 and Quiz 2.0 (Optional Quiz 1.1 and Quiz 2.1) = max (Quiz 1.x) + max (Quiz 2.x) 10 = (2 10) = 2 paper reviews 10 = Classroom and Piazza participation Option-II: 30 = (3 10) = 3 programming assignments 20 = (1 20) = max (Quiz 1.0, Quiz 1.1) 30 = (1 30) = 1 research project (weekly meetings) 10 = (2 5) = 2 paper reviews 10 = Classroom and Piazza participation Modern Memory Systems Biswabandan Panda, CSE@IITK 4
5 Let s Get Started Wait!!!! Latency,Bandwidth, Energy, and Power?? Modern Memory Systems Biswabandan Panda, CSE@IITK 5
6 Latency vs Bandwidth Latency vs Bandwidth, How they affect each other? Latency helps bandwidth but not vice versa. DRAM latency More # Accesses ~DRAM Bandwidth Bandwidth usually hurts latency Queues - Bandwidth Increases latency Modern Memory Systems Biswabandan Panda, CSE@IITK 6
7 Bandwidth problems can be cured with money. Latency problems are harder because the speed of light is fixed you can t bribe God Modern Memory Systems Biswabandan Panda, CSE@IITK 7
8 Energy vs Power Energy: Measure of using power for some time Power: Instantaneous rate of energy transfer Watt Design 1 Design 2 Power: Height of the curve Energy: Area under the curve Time Modern Memory Systems Biswabandan Panda, CSE@IITK 8
9 Let s Bring Latency. Source: Powerbar Power efficiency = Performance/watt Energy efficiency = Performance/Joule Modern Memory Systems Biswabandan Panda, CSE@IITK 9
10 Execution time, Performance, CPI, IPC BASICS Latency & Bandwidth, Amdahl s Law Instruction Pipelining, Branch Prediction LOAD/STORE(s), ROB, LQ/SQ Superscalar, SMT Processor Modern Memory Systems Biswabandan Panda, CSE@IITK 10
11 Execution Time Execution Time = Time Program Executed Instructions not static ones: Driven by: Algorithm, ISA, and Compilers Instruction?? = Instructions X Program Driven by: ISA and Processor Organization Cycle?? = Instructions Cycles X X Program Instruction = Instructions Cycles X X Program Instruction Time Cycle (Iron law) Driven by Technology Modern Memory Systems Biswabandan Panda, CSE@IITK 11
12 Cycles Per Instruction (CPI) Depends on Depth of Processor pipeline, Instruction level Parallelism Accuracy of branch predictor Latency of Caches, TLBs, and DRAM Many others. Modern Memory Systems Biswabandan Panda, 12
13 Performance Measurement Performance of a machine in terms of execution time, throughput? Latency is additive, throughput is not 6 hours at 30 km/hour + 2 hours at 90 km/hr Total latency: 8 hrs Total throughput: You find out Why you need to measure what you measure? Modern Memory Systems Biswabandan Panda, CSE@IITK 13
14 Benchmark Suites SPEC CPU SPECWeb PARSEC and SPLASH Bigdatabench Collection of relevant programs (binaries) Mobile Workloads Modern Memory Systems Biswabandan Panda, 14
15 Measuring Performance Pick a relevant benchmark suite Measure IPC of each program Summarize the performance using: Arithmetic Mean (AM) Geometric Mean (GM) Which one to choose? Harmonic Mean (HM) Modern Memory Systems Biswabandan Panda, CSE@IITK 15
16 An Example IMTEL ABM AND App. one App. two App. three Which machine is better over IMTEL and why? Modern Memory Systems Biswabandan Panda, 16
17 An Example Normalized Performance (Speedup) ABM AND App. one App. two App. three A.M G.M H.M Source: Pinterest Modern Memory Systems Biswabandan Panda, CSE@IITK 17
18 X Y App App Normalized to X X Y App AM on Ratios App AM Normalized to Y X Y App App AM Y is 50 times faster than X X is 50 times faster than Y Modern Memory Systems Biswabandan Panda, CSE@IITK 18
19 When to use What? Do not use A.M. on normalized numbers Use G.M. for normalized numbers Communications of the ACM, March 1986, pp Modern Memory Systems Biswabandan Panda, 19
20 Amdahl s Law Source: The Guardian ExTimenew ExTimeold 1 Fractionenhanced Fraction enhanced Speedup enhanced Speedup overall ExTime ExTime old new 1 Fraction enhanced 1 Fraction Speedup enhanced enhanced Modern Memory Systems Biswabandan Panda, CSE@IITK 20
21 Amdahl s Law Which one will provide better overall speedup? A. Small speedup on the large fraction of execution time. B. Large speedup on the small fraction of execution time. C. Does not matter. Depends on the difference between small and large. Mostly it is A. Amdahl s law for parallel processing Modern Memory Systems Biswabandan Panda, CSE@IITK 21
22 Cycles Per Instruction Depends on Depth of Processor pipeline, Instruction level Parallelism Accuracy of branch predictor Latency of Caches, TLBs, and DRAM Many others. Modern Memory Systems Biswabandan Panda, 22
23 WB Data Instruction Pipelining Instruction Fetch Instruction Decode Register Fetch Execute Eff. Addr. Calc. Memory Access Write Back Next PC 4 Adder Next SEQ PC RS1 Next SEQ PC Zero? MUX Address Memory IF/ID RS2 Reg File ID/EX MUX MUX ALU EX/MEM Data Memory MEM/WB MUX Imm Sign Extend RD RD RD Modern Memory Systems Biswabandan Panda, CSE@IITK 23
24 Fetch Stage Instruction Fetch Next PC Address 4 Adder Memory IF/ID IR <= mem[pc] PC <= PC + 4 What is the first instruction that is fetched when a system is power-up? Modern Memory Systems Biswabandan Panda, CSE@IITK 24
25 Decode Stage Instruction Fetch Instruction Decode Register Fetch Next SEQ PC Next PC Address 4 Adder Memory IF/ID RS1 RS2 Reg File ID/EX A <= Reg[IR rs ] B <= Reg[IR rt ] Imm Sign Extend RD Modern Memory Systems Biswabandan Panda, CSE@IITK 25
26 Execute Stage Instruction Fetch Instruction Decode Register Fetch Execute Eff. Addr. Calc. Next PC 4 Adder Next SEQ PC RS1 Next SEQ PC Zero? Address Memory IF/ID RS2 Reg File ID/EX MUX MUX ALU EX/MEM rslt <= A op IRop B Imm Sign Extend RD RD Modern Memory Systems Biswabandan Panda, CSE@IITK 26
27 Memory Stage Instruction Fetch Instruction Decode Register Fetch Execute Eff. Addr. Calc. Memory Access Next PC 4 Adder Next SEQ PC RS1 Next SEQ PC Zero? MUX Address Memory IF/ID RS2 Reg File ID/EX MUX MUX ALU EX/MEM Data Memory MEM/WB WB <= rslt Imm Sign Extend RD RD RD Modern Memory Systems Biswabandan Panda, CSE@IITK 27
28 WB Data Writeback Stage Instruction Fetch Next PC Address 4 Adder Memory Instruction Decode Register Fetch IF/ID Next SEQ PC RS1 RS2 Reg File ID/EX Execute Eff. Addr. Calc. Next SEQ PC MUX MUX Zero? ALU EX/MEM Memory Access MUX Data Memory MEM/WB Writeback MUX How many stages in commercial processors? Reg[IR rd ] <= WB Imm Sign Extend RD RD RD Modern Memory Systems Biswabandan Panda, CSE@IITK 28
29 Speedup with Pipelining t0 t1 t2 t3 t4 t5 t6 t7 t8 I1 IF 1 ID 1 EX 1 MA 1 WB 1 I2 IF 2 ID 2 EX 2 MA 2 WB 2 I3 IF 3 ID 3 EX 3 MA 3 WB 3 I4 IF 4 ID 4 EX 4 MA 4 WB 4 I5 IF 5 ID 5 EX 5 MA 5 WB 5 Speedup achieved with pipelining? 25/9 What about THE ideal 5-stage pipeline for a billion of instructions? ~5 Modern Memory Systems Biswabandan Panda, CSE@IITK 29
30 Real World (! Ideal one) Pipeline hazards Structural I1 I2 Next instruction can not proceed through pipeline as expected in the ideal case I1 and I2 conflicting for a resource: Memory, Caches Data Control I1 I2 X=X+1 Y=X+2 I1 If(X==2) I2 else I3 I2 dependent on data value generated by I1 I2 dependent on I1, where I1 is a branch instruction Modern Memory Systems Biswabandan Panda, CSE@IITK 30
31 ALU ALU ALU ALU ALU Structural Hazard Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Load Ifetch Reg DMem Reg Instr 1 Ifetch Reg DMem Reg Instr 2 Ifetch Reg DMem Reg Instr 3 Ifetch Reg DMem Reg Instr 4 Ifetch Reg DMem Reg Adapted from Computer Architecture: A Quantitative Approach, Copyright 2005 UCB Modern Memory Systems Biswabandan Panda, CSE@IITK 31
32 ALU ALU ALU ALU ALU Data Hazard add r1,r2,r3 Ifetch Reg DMem Reg sub r4,r1,r3 Ifetch Reg DMem Reg and r6,r1,r7 Ifetch Reg DMem Reg or r8,r1,r9 Ifetch Reg DMem Reg xor r10,r1,r11 Ifetch Reg DMem Reg Adapted from Computer Architecture: A Quantitative Approach, Copyright 2005 UCB Modern Memory Systems Biswabandan Panda, CSE@IITK 32
33 ALU ALU ALU ALU ALU Control Hazard beq r1,r3, L1 Ifetch Reg DMem Reg and r2,r3,r5 Ifetch Reg DMem Reg or r6,r1,r7 Ifetch Reg DMem Reg add r8,r1,r9 Ifetch Reg DMem Reg L1: xor r10,r1,r11 Ifetch Reg DMem Reg Adapted from Computer Architecture: A Quantitative Approach, Copyright 2005 UCB Modern Memory Systems Biswabandan Panda, CSE@IITK 33
34 Branch Predictors A hardware structure that predicts T/NT of a branch instruction Why? Branch miss penalty ~ 20 cycles Used in stage?? F/D/E?? Static Prediction Always T/NT Dynamic Prediction Exploits the dynamic nature of code. Modern Memory Systems Biswabandan Panda, CSE@IITK 34
35 Dynamic Branch Predictors TAGE, Perceptron, Tournament, Agree, Alloyed, Hybrid, Neural, Correlating, Skewed, O-GHEL, Franken, Modern Memory Systems Biswabandan Panda, 35
36 2-bit Predictor T NT Predict T T T NT Predict T PC Predict NT NT Predict NT T NT Modern Memory Systems Biswabandan Panda, CSE@IITK 36
37 Buzzwords from Processor Design ROB, LSQ, Register renaming, Superscalar, Tomasulo Algorithm, IQ, Register data flow, Reservation stations, Load bypassing (forwarding) Modern Memory Systems Biswabandan Panda, 37
38 O3-101 Modern Memory Systems Biswabandan Panda, 38
39 SMT-101 Modern Memory Systems Biswabandan Panda, 39
40 Intel s Hyperthreading L1 Cache Store Buffer I-Fetch Uop Queue Rename Queue Sched Register Read Execute Register Write Commit Prog. Counters Trace Cache Allocate Registers Data Cache Registers Reorder Buffer... Modern Memory Systems Biswabandan Panda, CSE@IITK 40
41 CPU-Memory Gap CPU Latency Bandwidth DRAM Modern Memory Systems Biswabandan Panda, 41
42 CPU-Memory Gap Modern Memory Systems Biswabandan Panda, 42
43 CPU-Memory Gap A 4-issue processor running on 4GHz DRAM latency: 100 ns #instructions executed during one DRAM access?? 1600 Modern Memory Systems Biswabandan Panda, CSE@IITK 43
44 Memory Hierarchy Reduces the gap by using small and fast caches Exploits temporal and spatial localities P(access,t) Registers On-Chip Cache (L1/L2) On-Chip (L3/L4) Off-chip DRAM Disk address Adapted from Copyright 2005 UCB Program access a relatively small portion of the address space at any instant of time. Example: 90% of time in 10% of the code Modern Memory Systems Biswabandan Panda, CSE@IITK 44
45 Cache Events Data Data Core CACHE Address Address Hit (found in cache)/miss? Compulsory Miss Replacement Capacity Miss Conflict Miss Modern Memory Systems Biswabandan Panda, 45
46 Access Patterns Instruction fetches: Loops Address Sub-routine call Scalars and Vectors Time Source: 6.823, MIT Modern Memory Systems Biswabandan Panda, 46
47 Memory Address (one dot per access) Locality Temporal Locality Spatial Locality Donald J. Hatfield, Jeanette Gerald: Program Restructuring for Virtual Memory. IBM Systems Journal 10(3): (1971) Source: 6.823, MIT Modern Memory Systems Biswabandan Panda, 47
48 Placement Policy Block # Set # Cache Fully (2-way) Set Direct Associative Associative Mapped Modern Memory Systems Biswabandan Panda, CSE@IITK 48
49 Mapping n-bit Address Tag Index Offset Used for tag compare Selects the set Selects the byte in the block Tag Decreasing associativity Direct mapped (only one way) Smaller tags Index Increasing associativity Block offset Fully associative (only one set) Tag is all the bits except block offset Offset Index Tag Width log 2 (block size) log 2 (number of sets) n-offset-index Modern Memory Systems Biswabandan Panda, CSE@IITK 49
50 Direct Mapped Cache Tag Index Block Offset t V Tag k Data Block b 2 k lines = t HIT Data Word or Byte Source: 6.823, MIT Modern Memory Systems Biswabandan Panda, CSE@IITK 50
51 2-way Set Associative Tag Index Block Offset b t V k Tag Data Block V Tag Data Block t = = Data Word or Byte HIT Source: 6.823, MIT Modern Memory Systems Biswabandan Panda, CSE@IITK 51
52 4-way Tag Index V Tag Data V Tag Data V Tag Data V Tag Data x1 select Hit Modern Memory Systems Biswabandan Panda, CSE@IITK 52 Data
53 Fully-associative V Tag t = Data Block Block Off. Tag b t = = Data Word or Byte HIT Source: 6.823, MIT Modern Memory Systems Biswabandan Panda, CSE@IITK 53
54 Cache Misses Compulsory: first access to a block (cold start) misses Infinite Cache?? Capacity: Limited cache size too small to keep the working set Infinite Cache?? Conflict: Collisions because of associativity Fully-associative?? Modern Memory Systems Biswabandan Panda, CSE@IITK 54
55 Average Memory Access Time Average memory access time = Hit time + Miss rate x Miss penalty Cache Optimizations: Way-prediction, multi-level caches, prefetching, banked cache, critical word first, non-blocking cache, victim cache Modern Memory Systems Biswabandan Panda, CSE@IITK 55
56 #levels in cache, private/shared? Try to Find out in Your Laptop Cache size, associativity, block size Hit/Miss Latencies Replacement Policies Modern Memory Systems Biswabandan Panda, 56
57 Additional Readings Modern Memory Systems Biswabandan Panda, 57
58 For Programming Assignments Start Early: From Day 1 to Day n-1 You have to submit a report containing results/insights and your code You have to present your findings through a 8+2 mins of presentation. Cheating is easy. Try something more challenging, like being faithful. Modern Memory Systems Biswabandan Panda, CSE@IITK 58
59 Tutorial 1 Modern Memory Systems Biswabandan Panda, CSE@IITK 59
60 Next Lecture Welcome to CS698Y Modern Memory Systems Biswabandan Panda, 60
Computer Systems Architecture Spring 2016
Computer Systems Architecture Spring 2016 Lecture 01: Introduction Shuai Wang Department of Computer Science and Technology Nanjing University [Adapted from Computer Architecture: A Quantitative Approach,
COSC 6385 Computer Architecture - Pipelining
COSC 6385 Computer Architecture - Pipelining Fall 2006 Some of the slides are based on a lecture by David Culler, Instruction Set Architecture Relevant features for distinguishing ISA s Internal storage
HY425 Lecture 05: Branch Prediction
HY425 Lecture 05: Branch Prediction Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS October 19, 2011 Dimitrios S. Nikolopoulos HY425 Lecture 05: Branch Prediction 1 / 45 Exploiting ILP in hardware
Computer Architecture Spring 2016
Computer Architecture Spring 2016 Lecture 02: Introduction II Shuai Wang Department of Computer Science and Technology Nanjing University Pipeline Hazards Major hurdle to pipelining: hazards prevent the
LECTURE 3: THE PROCESSOR
LECTURE 3: THE PROCESSOR Abridged version of Patterson & Hennessy (2013):Ch.4 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU
Computer Architecture
Lecture 3: Pipelining Iakovos Mavroidis Computer Science Department University of Crete 1 Previous Lecture Measurements and metrics : Performance, Cost, Dependability, Power Guidelines and principles in
Pipelining! Advanced Topics on Heterogeneous System Architectures. Politecnico di Milano! Seminar DEIB! 30 November, 2017!
Advanced Topics on Heterogeneous System Architectures Pipelining! Politecnico di Milano! Seminar Room @ DEIB! 30 November, 2017! Antonio R. Miele! Marco D. Santambrogio! Politecnico di Milano! 2 Outline!
Advanced Computer Architecture
ECE 563 Advanced Computer Architecture Fall 2009 Lecture 3: Memory Hierarchy Review: Caches 563 L03.1 Fall 2010 Since 1980, CPU has outpaced DRAM... Four-issue 2GHz superscalar accessing 100ns DRAM could
ECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 27: Midterm2 review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Midterm 2 Review Midterm will cover Section 1.6: Processor
EI338: Computer Systems and Engineering (Computer Architecture & Operating Systems)
EI338: Computer Systems and Engineering (Computer Architecture & Operating Systems) Chentao Wu 吴晨涛 Associate Professor Dept. of Computer Science and Engineering Shanghai Jiao Tong University SEIEE Building
ECE/CS 552: Pipelining to Superscalar Prof. Mikko Lipasti
ECE/CS 552: Pipelining to Superscalar Prof. Mikko Lipasti Lecture notes based in part on slides created by Mark Hill, David Wood, Guri Sohi, John Shen and Jim Smith Pipelining to Superscalar Forecast Real
Chapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
Department of Computer and IT Engineering University of Kurdistan. Computer Architecture Pipelining. By: Dr. Alireza Abdollahpouri
Department of Computer and IT Engineering University of Kurdistan Computer Architecture Pipelining By: Dr. Alireza Abdollahpouri Pipelined MIPS processor Any instruction set can be implemented in many
Lecture-14 (Memory Hierarchy) CS422-Spring
Lecture-14 (Memory Hierarchy) CS422-Spring 2018 Biswa@CSE-IITK The Ideal World Instruction Supply Pipeline (Instruction execution) Data Supply - Zero-cycle latency - Infinite capacity - Zero cost - Perfect
Pipelining to Superscalar
Pipelining to Superscalar ECE/CS 752 Fall 207 Prof. Mikko H. Lipasti University of Wisconsin-Madison Pipelining to Superscalar Forecast Limits of pipelining The case for superscalar Instruction-level parallel
Improve performance by increasing instruction throughput
Improve performance by increasing instruction throughput Program execution order Time (in instructions) lw $1, 100($0) fetch 2 4 6 8 10 12 14 16 18 ALU Data access lw $2, 200($0) 8ns fetch ALU Data access
Agenda. EE 260: Introduction to Digital Design Memory. Naive Register File. Agenda. Memory Arrays: SRAM. Memory Arrays: Register File
EE 260: Introduction to Digital Design Technology Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa 2 Technology Naive Register File Write Read clk Decoder Read Write 3 4 Arrays:
Computer and Information Sciences College / Computer Science Department Enhancing Performance with Pipelining
Computer and Information Sciences College / Computer Science Department Enhancing Performance with Pipelining Single-Cycle Design Problems Assuming fixed-period clock every instruction datapath uses one
COMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 Edition th The Hardware/Software Interface Chapter 4 The Processor 4.1 Introduction Introduction CPU performance factors Instruction count CPI and Cycle time Determined
Pipelining Analogy. Pipelined laundry: overlapping execution. Parallelism improves performance. Four loads: Non-stop: Speedup = 8/3.5 = 2.3.
Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup =2n/05n+15 2n/0.5n 1.5 4 = number of stages 4.5 An Overview
CMSC 411 Computer Systems Architecture Lecture 6 Basic Pipelining 3. Complications With Long Instructions
CMSC 411 Computer Systems Architecture Lecture 6 Basic Pipelining 3 Long Instructions & MIPS Case Study Complications With Long Instructions So far, all MIPS instructions take 5 cycles But haven't talked
Data Hazards Compiler Scheduling Pipeline scheduling or instruction scheduling: Compiler generates code to eliminate hazard
Data Hazards Compiler Scheduling Pipeline scheduling or instruction scheduling: Compiler generates code to eliminate hazard Consider: a = b + c; d = e - f; Assume loads have a latency of one clock cycle:
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. 5 th. Edition. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
Lecture 3. Pipelining. Dr. Soner Onder CS 4431 Michigan Technological University 9/23/2009 1
Lecture 3 Pipelining Dr. Soner Onder CS 4431 Michigan Technological University 9/23/2009 1 A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP take pair)
Pipeline Overview. Dr. Jiang Li. Adapted from the slides provided by the authors. Jiang Li, Ph.D. Department of Computer Science
Pipeline Overview Dr. Jiang Li Adapted from the slides provided by the authors Outline MIPS An ISA for Pipelining 5 stage pipelining Structural and Data Hazards Forwarding Branch Schemes Exceptions and
Lecture 4: Instruction Set Architectures. Review: latency vs. throughput
Lecture 4: Instruction Set Architectures Last Time Performance analysis Amdahl s Law Performance equation Computer benchmarks Today Review of Amdahl s Law and Performance Equations Introduction to ISAs
Tutorial 11. Final Exam Review
Tutorial 11 Final Exam Review Introduction Instruction Set Architecture: contract between programmer and designers (e.g.: IA-32, IA-64, X86-64) Computer organization: describe the functional units, cache
" # " $ % & ' ( ) * + $ " % '* + * ' "
! )! # & ) * + * + * & *,+,- Update Instruction Address IA Instruction Fetch IF Instruction Decode ID Execute EX Memory Access ME Writeback Results WB Program Counter Instruction Register Register File
Chapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
14:332:331. Week 13 Basics of Cache
14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 13 Basics of Cache [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] 331 Week131 Spring 2006
Lecture 29 Review" CPU time: the best metric" Be sure you understand CC, clock period" Common (and good) performance metrics"
Be sure you understand CC, clock period Lecture 29 Review Suggested reading: Everything Q1: D[8] = D[8] + RF[1] + RF[4] I[15]: Add R2, R1, R4 RF[1] = 4 I[16]: MOV R3, 8 RF[4] = 5 I[17]: Add R2, R2, R3
Page 1. Multilevel Memories (Improving performance using a little cash )
Page 1 Multilevel Memories (Improving performance using a little cash ) 1 Page 2 CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency Latency
Lecture: Out-of-order Processors
Lecture: Out-of-order Processors Topics: branch predictor wrap-up, a basic out-of-order processor with issue queue, register renaming, and reorder buffer 1 Amdahl s Law Architecture design is very bottleneck-driven
Modern Computer Architecture
Modern Computer Architecture Lecture3 Review of Memory Hierarchy Hongbin Sun 国家集成电路人才培养基地 Xi an Jiaotong University Performance 1000 Recap: Who Cares About the Memory Hierarchy? Processor-DRAM Memory Gap
Performance of Computer Systems. CSE 586 Computer Architecture. Review. ISA s (RISC, CISC, EPIC) Basic Pipeline Model.
Performance of Computer Systems CSE 586 Computer Architecture Review Jean-Loup Baer http://www.cs.washington.edu/education/courses/586/00sp Performance metrics Use (weighted) arithmetic means for execution
Full Datapath. Chapter 4 The Processor 2
Pipelining Full Datapath Chapter 4 The Processor 2 Datapath With Control Chapter 4 The Processor 3 Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory
Microarchitecture Overview. Performance
Microarchitecture Overview Prof. Scott Rixner Duncan Hall 3028 rixner@rice.edu January 18, 2005 Performance 4 Make operations faster Process improvements Circuit improvements Use more transistors to make
3/12/2014. Single Cycle (Review) CSE 2021: Computer Organization. Single Cycle with Jump. Multi-Cycle Implementation. Why Multi-Cycle?
CSE 2021: Computer Organization Single Cycle (Review) Lecture-10b CPU Design : Pipelining-1 Overview, Datapath and control Shakil M. Khan 2 Single Cycle with Jump Multi-Cycle Implementation Instruction:
Lecture 1: Introduction
Lecture 1: Introduction Dr. Eng. Amr T. Abdel-Hamid Winter 2014 Computer Architecture Text book slides: Computer Architec ture: A Quantitative Approach 5 th E dition, John L. Hennessy & David A. Patterso
10/19/17. You Are Here! Review: Direct-Mapped Cache. Typical Memory Hierarchy
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3 Instructors: Krste Asanović & Randy H Katz http://insteecsberkeleyedu/~cs6c/ Parallel Requests Assigned to computer eg, Search
Pipelining, Instruction Level Parallelism and Memory in Processors. Advanced Topics ICOM 4215 Computer Architecture and Organization Fall 2010
Pipelining, Instruction Level Parallelism and Memory in Processors Advanced Topics ICOM 4215 Computer Architecture and Organization Fall 2010 NOTE: The material for this lecture was taken from several
CENG 3531 Computer Architecture Spring a. T / F A processor can have different CPIs for different programs.
Exam 2 April 12, 2012 You have 80 minutes to complete the exam. Please write your answers clearly and legibly on this exam paper. GRADE: Name. Class ID. 1. (22 pts) Circle the selected answer for T/F and
CS 341l Fall 2008 Test #2
CS 341l all 2008 Test #2 Name: Key CS 341l, test #2. 100 points total, number of points each question is worth is indicated in parentheses. Answer all questions. Be as concise as possible while still answering
Microarchitecture Overview. Performance
Microarchitecture Overview Prof. Scott Rixner Duncan Hall 3028 rixner@rice.edu January 15, 2007 Performance 4 Make operations faster Process improvements Circuit improvements Use more transistors to make
Modern Computer Architecture
Modern Computer Architecture Lecture2 Pipelining: Basic and Intermediate Concepts Hongbin Sun 国家集成电路人才培养基地 Xi an Jiaotong University Pipelining: Its Natural! Laundry Example Ann, Brian, Cathy, Dave each
COSC4201 Pipelining. Prof. Mokhtar Aboelaze York University
COSC4201 Pipelining Prof. Mokhtar Aboelaze York University 1 Instructions: Fetch Every instruction could be executed in 5 cycles, these 5 cycles are (MIPS like machine). Instruction fetch IR Mem[PC] NPC
ECE 2300 Digital Logic & Computer Organization. Caches
ECE 23 Digital Logic & Computer Organization Spring 217 s Lecture 2: 1 Announcements HW7 will be posted tonight Lab sessions resume next week Lecture 2: 2 Course Content Binary numbers and logic gates
ECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 35: Final Exam Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Material from Earlier in the Semester Throughput and latency
Question 1: (20 points) For this question, refer to the following pipeline architecture.
This is the Mid Term exam given in Fall 2018. Note that Question 2(a) was a homework problem this term (was not a homework problem in Fall 2018). Also, Questions 6, 7 and half of 5 are from Chapter 5,
Computer Architecture CS372 Exam 3
Name: Computer Architecture CS372 Exam 3 This exam has 7 pages. Please make sure you have all of them. Write your name on this page and initials on every other page now. You may only use the green card
Control Hazards - branching causes problems since the pipeline can be filled with the wrong instructions.
Control Hazards - branching causes problems since the pipeline can be filled with the wrong instructions Stage Instruction Fetch Instruction Decode Execution / Effective addr Memory access Write-back Abbreviation
14:332:331 Pipelined Datapath
14:332:331 Pipelined Datapath I n s t r. O r d e r Inst 0 Inst 1 Inst 2 Inst 3 Inst 4 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be timed to accommodate
EECS151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: John Wawrzynek and Nick Weaver. Lecture 19: Caches EE141
EECS151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: John Wawrzynek and Nick Weaver Lecture 19: Caches Cache Introduction 40% of this ARM CPU is devoted to SRAM cache. But the role
Processor Architecture. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Processor Architecture Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Moore s Law Gordon Moore @ Intel (1965) 2 Computer Architecture Trends (1)
Lecture 2: Processor and Pipelining 1
The Simple BIG Picture! Chapter 3 Additional Slides The Processor and Pipelining CENG 6332 2 Datapath vs Control Datapath signals Control Points Controller Datapath: Storage, FU, interconnect sufficient
Lecture-13 (ROB and Multi-threading) CS422-Spring
Lecture-13 (ROB and Multi-threading) CS422-Spring 2018 Biswa@CSE-IITK Cycle 62 (Scoreboard) vs 57 in Tomasulo Instruction status: Read Exec Write Exec Write Instruction j k Issue Oper Comp Result Issue
Pipelining. Pipeline performance
Pipelining Basic concept of assembly line Split a job A into n sequential subjobs (A 1,A 2,,A n ) with each A i taking approximately the same time Each subjob is processed by a different substation (or
CS/CoE 1541 Mid Term Exam (Fall 2018).
CS/CoE 1541 Mid Term Exam (Fall 2018). Name: Question 1: (6+3+3+4+4=20 points) For this question, refer to the following pipeline architecture. a) Consider the execution of the following code (5 instructions)
The Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
CSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]
![CSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]](/thumbs/73/69213006.jpg "CSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]")
CSF Cache Introduction [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005] Review: The Memory Hierarchy Take advantage of the principle of locality to present the user with as much
Caches Part 1. Instructor: Sören Schwertfeger. School of Information Science and Technology SIST
CS 110 Computer Architecture Caches Part 1 Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's
Memory Hierarchies 2009 DAT105
Memory Hierarchies Cache performance issues (5.1) Virtual memory (C.4) Cache performance improvement techniques (5.2) Hit-time improvement techniques Miss-rate improvement techniques Miss-penalty improvement
Lecture 05: Pipelining: Basic/ Intermediate Concepts and Implementation
Lecture 05: Pipelining: Basic/ Intermediate Concepts and Implementation CSE 564 Computer Architecture Summer 2017 Department of Computer Science and Engineering Yonghong Yan yan@oakland.edu www.secs.oakland.edu/~yan
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 1 Instructors: Nicholas Weaver & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/ Components of a Computer Processor
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 3 Instructors: Krste Asanović & Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/ 10/19/17 Fall 2017 - Lecture #16 1 Parallel
Copyright 2012, Elsevier Inc. All rights reserved.
Computer Architecture A Quantitative Approach, Fifth Edition Chapter 3 Instruction-Level Parallelism and Its Exploitation 1 Branch Prediction Basic 2-bit predictor: For each branch: Predict taken or not
Pipelining. Ideal speedup is number of stages in the pipeline. Do we achieve this? 2. Improve performance by increasing instruction throughput ...
CHAPTER 6 1 Pipelining Instruction class Instruction memory ister read ALU Data memory ister write Total (in ps) Load word 200 100 200 200 100 800 Store word 200 100 200 200 700 R-format 200 100 200 100
Computer Architecture and System
Computer Architecture and System 2012 Chung-Ho Chen Computer Architecture and System Laboratory Department of Electrical Engineering National Cheng-Kung University Course Focus Understanding the design
COMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
Computer Architecture and System
Computer Architecture and System Chung-Ho Chen Computer Architecture and System Laboratory Department of Electrical Engineering National Cheng-Kung University Course Focus Understanding the design techniques,
Instruction Level Parallelism. Appendix C and Chapter 3, HP5e
Instruction Level Parallelism Appendix C and Chapter 3, HP5e Outline Pipelining, Hazards Branch prediction Static and Dynamic Scheduling Speculation Compiler techniques, VLIW Limits of ILP. Implementation
The Memory Hierarchy. Cache, Main Memory, and Virtual Memory (Part 2)
The Memory Hierarchy Cache, Main Memory, and Virtual Memory (Part 2) Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Cache Line Replacement The cache
Processor Architecture
Processor Architecture Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu)
CPU Pipelining Issues
CPU Pipelining Issues What have you been beating your head against? This pipe stuff makes my head hurt! L17 Pipeline Issues & Memory 1 Pipelining Improve performance by increasing instruction throughput
Full Datapath. Chapter 4 The Processor 2
Pipelining Full Datapath Chapter 4 The Processor 2 Datapath With Control Chapter 4 The Processor 3 Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory
Mo Money, No Problems: Caches #2...
Mo Money, No Problems: Caches #2... 1 Reminder: Cache Terms... Cache: A small and fast memory used to increase the performance of accessing a big and slow memory Uses temporal locality: The tendency to
CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!
CS654 Advanced Computer Architecture. Lec 2 - Introduction
CS654 Advanced Computer Architecture Lec 2 - Introduction Peter Kemper Adapted from the slides of EECS 252 by Prof. David Patterson Electrical Engineering and Computer Sciences University of California,
Limitations of Scalar Pipelines
Limitations of Scalar Pipelines Superscalar Organization Modern Processor Design: Fundamentals of Superscalar Processors Scalar upper bound on throughput IPC = 1 Inefficient unified pipeline
Lecture 9: More ILP. Today: limits of ILP, case studies, boosting ILP (Sections )
Lecture 9: More ILP Today: limits of ILP, case studies, boosting ILP (Sections 3.8-3.14) 1 ILP Limits The perfect processor: Infinite registers (no WAW or WAR hazards) Perfect branch direction and target
Processor (II) - pipelining. Hwansoo Han
Processor (II) - pipelining Hwansoo Han Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance Four loads: Speedup = 8/3.5 =2.3 Non-stop: 2n/0.5n + 1.5 4 = number
Lecture 11: SMT and Caching Basics. Today: SMT, cache access basics (Sections 3.5, 5.1)
Lecture 11: SMT and Caching Basics Today: SMT, cache access basics (Sections 3.5, 5.1) 1 Thread-Level Parallelism Motivation: a single thread leaves a processor under-utilized for most of the time by doubling
CS152 Computer Architecture and Engineering March 13, 2008 Out of Order Execution and Branch Prediction Assigned March 13 Problem Set #4 Due March 25
CS152 Computer Architecture and Engineering March 13, 2008 Out of Order Execution and Branch Prediction Assigned March 13 Problem Set #4 Due March 25 http://inst.eecs.berkeley.edu/~cs152/sp08 The problem
Advanced Computer Architecture
Advanced Computer Architecture Chapter 1 Introduction into the Sequential and Pipeline Instruction Execution Martin Milata What is a Processors Architecture Instruction Set Architecture (ISA) Describes
CMSC411 Fall 2013 Midterm 1
CMSC411 Fall 2013 Midterm 1 Name: Instructions You have 75 minutes to take this exam. There are 100 points in this exam, so spend about 45 seconds per point. You do not need to provide a number if you
CISC 662 Graduate Computer Architecture Lecture 6 - Hazards
CISC 662 Graduate Computer Architecture Lecture 6 - Hazards Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer
CS/CoE 1541 Exam 1 (Spring 2019).
CS/CoE 1541 Exam 1 (Spring 2019). Name: Question 1 (8+2+2+3=15 points): In this problem, consider the execution of the following code segment on a 5-stage pipeline with forwarding/stalling hardware and
TDT 4260 lecture 7 spring semester 2015
1 TDT 4260 lecture 7 spring semester 2015 Lasse Natvig, The CARD group Dept. of computer & information science NTNU 2 Lecture overview Repetition Superscalar processor (out-of-order) Dependencies/forwarding
Advanced Caching Techniques (2) Department of Electrical Engineering Stanford University
Lecture 4: Advanced Caching Techniques (2) Department of Electrical Engineering Stanford University http://eeclass.stanford.edu/ee282 Lecture 4-1 Announcements HW1 is out (handout and online) Due on 10/15
Pipelining. Maurizio Palesi
* Pipelining * Adapted from David A. Patterson s CS252 lecture slides, http://www.cs.berkeley/~pattrsn/252s98/index.html Copyright 1998 UCB 1 References John L. Hennessy and David A. Patterson, Computer
Caches. Hiding Memory Access Times
Caches Hiding Memory Access Times PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U X C O N T R O L ALU CTL INSTRUCTION FETCH INSTR DECODE REG FETCH EXECUTE/ ADDRESS CALC MEMORY
Show Me the $... Performance And Caches
Show Me the $... Performance And Caches 1 CPU-Cache Interaction (5-stage pipeline) PCen 0x4 Add bubble PC addr inst hit? Primary Instruction Cache IR D To Memory Control Decode, Register Fetch E A B MD1
1. Truthiness /8. 2. Branch prediction /5. 3. Choices, choices /6. 5. Pipeline diagrams / Multi-cycle datapath performance /11
The University of Michigan - Department of EECS EECS 370 Introduction to Computer Architecture Midterm Exam 2 ANSWER KEY November 23 rd, 2010 Name: University of Michigan uniqname: (NOT your student ID
CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
MIPS An ISA for Pipelining
Pipelining: Basic and Intermediate Concepts Slides by: Muhamed Mudawar CS 282 KAUST Spring 2010 Outline: MIPS An ISA for Pipelining 5 stage pipelining i Structural Hazards Data Hazards & Forwarding Branch
Chapter 4 The Processor 1. Chapter 4A. The Processor
Chapter 4 The Processor 1 Chapter 4A The Processor Chapter 4 The Processor 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware
PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah
PERFORMANCE METRICS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Sept. 5 th : Homework 1 release (due on Sept.
CSEE 3827: Fundamentals of Computer Systems
CSEE 3827: Fundamentals of Computer Systems Lecture 21 and 22 April 22 and 27, 2009 martha@cs.columbia.edu Amdahl s Law Be aware when optimizing... T = improved Taffected improvement factor + T unaffected
Keywords and Review Questions
Keywords and Review Questions lec1: Keywords: ISA, Moore s Law Q1. Who are the people credited for inventing transistor? Q2. In which year IC was invented and who was the inventor? Q3. What is ISA? Explain
DHANALAKSHMI SRINIVASAN INSTITUTE OF RESEARCH AND TECHNOLOGY. Department of Computer science and engineering
DHANALAKSHMI SRINIVASAN INSTITUTE OF RESEARCH AND TECHNOLOGY Department of Computer science and engineering Year :II year CS6303 COMPUTER ARCHITECTURE Question Bank UNIT-1OVERVIEW AND INSTRUCTIONS PART-B