Organizational issues (I)

Transcription

1 COSC 6385 Computer Architecture Introduction and Organizational Issues Fall 2008 Organizational issues (I) Classes: Monday, 1.00pm 2.30pm, PGH 232 Wednesday, 1.00pm 2.30pm, PGH 232 Evaluation 25% homework 75% three quizzes ( 25% each) In case of questions: gabriel@cs.uh.edu Tel: (713) Office hours: PGH 524, Mo, Wed, 3pm-4pm or by appointment All slides available on the website: Videos of some lectures will be posted on Vnet and on the course web page 1

2 Organizational Issues (II) TA s for the course: Saber Feki, PGH 526, sfeki@cs.uh.edu Mohamad Chaarawi, PGH 526, mschaara@cs.uh.edu Tentative dates for the quizzes: Monday, September 29 th Monday, October 27 nd Wednesday, December 3 rd Homework Announced on September 22 nd Due on October 8th Contents Textbook: John L. Hennessy, David A. Patterson Computer Architecture A Quantitative Approach 4 th Edition Morgan Kaufmann Publishers 2

3 Contents (II) Most of chapters 1 to 5 Appendix A, B, C Selected sections regarding Storage systems Vector Processors Selected literature to multi-core processors Selected literature to virtualization Contents(III) Aug. 25 Aug. 27 Sep. 1 Sep. 3 Sep. 8 Sep. 10 Sep. 15 Sep. 17 Sep. 22 Sep. 24 Sep. 29 Oct. 1 Oct. 6 Oct. 8 Oct. 13 Oct. 15 Oct. 20 Overview, Motivation, Organization Performance Measurement Labor day, no lectures Instruction Set Architectures (online) Memory Hierarchy (I) (online) Memory Hierarchy (II) (online) Pipelining (I) Pipelining (II) Homework announcement Recap for 1st quiz 1st quiz Tomasolu's algorithm Dynamic branch prediction Hardware based speculation Discussion of 1st quiz ILP with software approaches Recap for 2nd quiz Oct. 22 Oct. 27 Oct. 29 Nov. 3 Nov. 5 Nov. 10 Nov. 12 Nov. 17 Nov. 19 Nov. 24 Nov. 26 Dec. 1 Dec. 3 Multi-processor systems (I) (online) 2nd quiz Multi-processor systems (II) Multi-processor systems (III) Virtualization File I/O Discussion of 2nd quiz Vector processors Networking/cancel class recap for 3rd quiz Thanksgiving holiday, no class History of Computers 3rd Quiz 3

4 Why learning about Computer Architecture? for (i=0; i<n; i++ ) { c[i] = a[i] + b[i]; Every loop iteration requires 3 memory operations 2 loads 1 store For a micro-processor having a frequency of 2 GHz this requires 9 1 3* 4Bytes * 2*10 s = 24GBytes / s to satisfy one Floating Point Unit (FPU) Most modern processors have 2 FPUs and 2 IUs which can work in parallel Memory technology ( DDR: Double Data Rate SDRAM Bandwidth of a memory module with SB SB max SB BUS f BUS max = SBBus * fbus* Op/ Cycle : max. memory bandwidth : Bandwidth of the memory bus (64 Bit = 8 Bytes) : Frequency of the memory bus 4

5 Name Memory bandwidth Frequency of memory bus (MHz) max. bandwidth PC100 SDRAM MB/s PC133 SDRAM GB/s PC1600 DDR GB/s PC2100 DDR GB/s PC2700 DDR GB/s PC3200 DDR GB/s PC3700 DDR GB/s PC4200 DDR GB/s Memory modules (cont.) Dual Channel Memory: 2 I/O Channels between memory controller und memory module DDR2: further evolution of the DDR technology uses 1.8 Volts vs. 2.5 Volts technology larger capacity of the chips higher frequency Name Frequency of memory bus Bandwidth of a module Dual Channel DDR2 bandwidth PC MHz 3.2 GB/s 6.4 GB/s PC MHz 4.2 GB/s 8.4 GB/s PC MHz 5.3 GB/s 10.6 GB/s PC MHz 6.4 GB/s 12.8 GB/s 5

6 Memory hierarchies Backup (tape) Size TB, PT Access time [cycles] Primary data storage (disk) ~ 100 GB > 10 6 main memory ~ 1-4 GB Caches ~ 1-4 MB 2 50 Register < 256 Words 1-2 Memory hierarchies Do I have to care about memory hierarchies? Example: Matrix-multiply of two dense matrices Trivial code for ( i=0; i<dim; i++ ) { for ( j=0; j<dim; j++ ) { for ( k=0; k<dim; k++) { c[i][j] += a[i][k] * b[k][j]; 6

7 Matrix-multiply Performance of the trivial implementation on an 2.2 GHz AMD Opteron with 2 GB main memory 1 MB 2 nd level cache Matrix dimension Execution time [sec] Performance [MFLOPS] 256x x Matrix-multiply (II) Peak performance of the processor 2 * (2.2 * 10 9 ) Floating point operations/sec = 4.4 * 10 9 = 4.4 GFLOPS Number of floating point units Frequency of the processor assuming that each FPU can finish an operation per cycle Theoretical floating point peak performance of the processor Where are the missing FLOPS between theoretical peek and achieved performance? Memory wait time 7

8 Blocked code for ( i=0; i<dim; i+=block ) { for ( j=0; j<dim; j+=block ) { for ( k=0; k<dim; k+=block) { for (ii=i; ii<(i+block); ii++) { for (jj=j; jj<(j+block); jj++) { for (kk=k; kk<(k+block);kk++) { c[ii][jj] += a[ii][kk] * b[kk][jj]; Matrix dimension Performance of the blocked code block Execution time [sec] Performance [MFLOPS] trivial [MFLOPS] 256x x

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10 Top 500 List ( 10

11 Top 500 List IBM Roadrunner First computer to surpass the 1 Petaflop (2 50 FLOPS ) barrier Installed at Los Alamos National Laboratories Hybrid Architecture 13,824 AMD Opteron cores 116,640 IBM PowerXCell 8i cores Costs: $120 million 11

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