COSC 6385 Computer Architecture - Review for the 2 nd Quiz

Transcription

1 COSC 6385 Computer Architecture - Review for the 2 nd Quiz Fall 2006

2 Covered topic area End of section 3 Multiple issue Speculative execution Limitations of hardware ILP Section 4 Vector Processors (Appendix G) Quiz will mainly consist of knowledge questions (80%- 100%!) Only calculation might include something with N 1/2 or N α

3 Multi-issue Why issuing multiple instructions? What are the two possible flavor of multi-issue processors? For Superscalar architectures: What is an issue packet? What is the additional complication introduced by an issue packet and how is it typically solved

4 Hardware based speculation What is the difference between branch prediction and speculative execution? What is the extension to Tomasolu s Algorithm which has to be introduced in order to incorporate speculative execution? What is a reorder buffer what is its function in Tomasolu s Algorithm? How does the reorder buffer handle a Correct prediction? An incorrect prediction?

5 Limitations of hardware ILP Name four limits for hardware based dynamic ILP

6 Software ILP What is the loop overhead? What is the purpose of code rescheduling? How does loop unrolling work? Advantages? Disadvantages? Why does the compiler has to create two loops out of one when introducing loop unrolling? Name three static branch prediction schemes used by compilers

7 Detecting loop level parallelism What is a loop-carried dependence? If you give you a simple loop, can you tell me whether there is a loop-carried dependence and if yes in which variable? Can a loop containing a recursion be parallelized? Explain the what the Greatest Common Divisor Test does/is

8 Eliminating dependencies What is copy propagation? How does tree height reduction work? Explain the main idea behind software pipelining Can you describe in 2 sentences: What is global scheduling? What is Trace scheduling?

9 Conditional instructions What is a conditional instruction? What are the two options for implementing conditional instructions and what are advantages and disadvantages of both approaches? What are the limitations of conditional instructions?

10 Compiler based speculation What are the four options for handling exceptions when applying compiler based speculation? Can you explain how these four methods work generally? Discuss the advantages and disadvantages of software vs. hardware based speculation

11 Vector processors What is the main idea behind a vector processor and what is its major advantage compared to a non-vector processor Given a simple code sequence, can you determine Which instructions can form a convoy How many chimes it takes to execute the convoy? Explain what the start-up overhead of a pipeline is and how this is limiting the performance of any processor How do vector processors handle arbitrary length of vectors? Assuming that a vector processor utilizes multiple banks Explain why the vector stride has an impact on the performance of a vector instruction What is the worst case scenario with respect to vector strides/memory banks and why?

12 Vector processors How does chaining work? How do vector processors implement conditional instructions How do vector processors support indirect addressing as occurring when using sparse matrices How can the throughput of a vector unit be improved? How can the start-up costs of a pipelining be improved?