ADVANCED COMPUTER ARCHITECTURES

Transcription

1 ADVANCED COMPUTER ARCHITECTURES AA 2014/2015 Second Semester Prof. Cristina Silvano Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB) Politecnico di Milano

2 Goals of the ACA course Provide an overview of the most recent and advanced computer architectures Introduce the basic micro-architectural mechanisms found in modern microprocessor architectures Provide the reasoning behind the adoption of advanced computer architectures Cristina Silvano Politecnico di Milano - 2 -

3 ADVANCED COMPUTER ARCHITECTURES: AN OVERVIEW Cristina Silvano Politecnico di Milano -3- March 2012

4 Advanced Computer Architectures: Supercomputers The first supercomputer reaching the Petascale peak performance (10 15 Flops) was installed in Research on supercomputing is pushing towards the Exascale (10 18 Flops) to be reached in Cristina Silvano Politecnico di Milano -4- March 2013

5 Top500 ranking of the world s most powerful supercomputers No. 1 Tianhe-2 reaches PetaFlops (Linpack performance) 54.9 PetaFlops peak performance with 17.8 MW power dissipation Site: National Super Computer Center in Guangzhou (China) No. 2 Titan: PetaFlops (Linpack performance) PetaFlops (peak performance) with 8.2MW power dissipation Site: Oak Ridge National Laboratory (USA) Both Tianhe-2 and Titan employ accelerator/co-processor technology Cristina Silvano Politecnico di Milano -5- March 2013

6 No. 2 TITAN Cray XK7, Opteron 2.2GHz, NVIDIA K20X Cristina Silvano Politecnico di Milano -6- March 2012

7 Exascale supercomputers To reach 20 MW Exascale supercomputer projected to 2020, current supercomputers must achieve energy efficiency pushing towards a goal of 50 GigaFlops/W No.1 Tianhe-2 delivers 1.9 GigaFlops/W resulting only 40th in the Green500 list ranking supercomputers by their energy efficiency. Today most green supercomputer in Green500 achieves 4.5 GigaFlops/W The top 17 positions of Green500 are currently occupied by heterogeneous computing systems This dominance will become a trend for the next coming years to reach the target of 20 MW Exascale supercomputer Cristina Silvano Politecnico di Milano -7- March 2013

8 US Dept. of Energy recently announced Summit and Sierra supercomputers Cristina Silvano Politecnico di Milano -8- March 2013

9 Applications driving the demand for more computing performance Astrophysics Climate Biology Business Analytics Cristina Silvano Politecnico di Milano -9- March 2012

10 Advanced Computer Architectures: Intel Core i7-3770t Processor (Nehalem, up to 3.70 GHz) # of Cores 4 # of Threads 8 160mm² 22nm 1.40 billion transistors. Clock Speed Max Turbo Frequency Intel Smart Cache Instruction Set Instruction Set Extensions Embedded Options Available Lithography Max TDP 2.5 GHz 3.7 GHz 8 MB 64-bit SSE4.1/4.2, AVX No 22 nm 45 W Recomm. Customer Price TRAY: $ Max Memory Size Memory Types 32 GB DDR3-1333/1600 Cristina Silvano Politecnico di Milano # of Memory Channels 2 Max Memory Bandwidth 25.6 GB/s

11 Advanced Computer Architectures: Smart Phones Cristina Silvano Politecnico di Milano

12 ARM Cortex-A8 core processor in Apple A4 System-on-Chip Based on the ARMv7 architecture It s a dual-issue in-order execution design The Apple A4 at 1 GHz (45nm manufactured by Samsung from March 2010 to present), a System-on-Chip that combines an ARM Cortex-A8 and a PowerVR GPU, is in the: Original ipad, April 2010 iphone4: June 2010 (Black; GSM), February 2011 (Black; CDMA), April 2011 (White; GSM & CDMA) ipod Touch (4th generation): September 2010 (Black model), October 2011 (White model) Apple TV (2nd generation): Sept

13 ARM Cortex-A9 MP core processor in Apple A5 System-on-Chip Based on the ARMv7 architecture It s a dual-issue in-order execution design The Apple A5 at 1 GHz (45nm to 32 nm manufactured by Samsung from March 2011 to present), a System-on-Chip that combines a dual core ARM Cortex-A9 with NEON SIMD accelerator and a dual core PowerVR GPU, is in the: ipad 2 (A5 dual-core 45 nm) March 2011; (A5 dual-core 32 nm) March 2012 iphone 4S (A5 dual-core 45 nm) October 2011 Apple TV 3rd generation (A5 single-core, 32 nm) March 2012 ipod Touch 5th generation (A5 dual-core 32 nm) October 2012 ipad Mini (A5 dual-core 32 nm) November

14 Apple A6 System-on-Chip Apple A6 SoC was introduced on Sept for the iphone 5 Apple states that it is up to twice as fast and has up to twice the graphics power compared to its predecessor the Apple A5 The A6 uses a 1.3 GHz custom Apple-designed ARMv7 based dual-core CPU, called Swift, and an integrated triple-core PowerVR SGX 543MP3 GPU. The A6 chip for iphone 5 incorporates 1GB of LPDDR RAM and provides double the memory capacity of iphone4s while increasing the theoretical memory bandwidth from 6.4 GB/s to 8.5 GB/s. 14

15 Apple A6 System-on-Chip ARMv7s ISA dual core Triple-core PowerVR SGX 543MP3 GPU 1MB L2 cache 1.3 GHz 32nm Samsung 96.71mm 2 (22% smaller than A5) Cristina Silvano Politecnico di Milano

16 Apple A7 System-on-Chip Apple A7 is a 64-bit SoC introduced on Sept for the iphone 5S Apple states that it is up to twice as fast and has up to twice the graphics power compared to its predecessor the Apple A6. The A7 features an Apple-designed 64-bit GHz ARMv8-A dual-core CPU, called Cyclone, and an integrated GPU PowerVR G6430 in a four cluster configuration The A7 has a per-core L1 cache of 64KB for data and 64 KB for instructions, a L2 cache of 1MB shared by both CPU cores, and a 4 MB L3 cache that services the entire SoC. Compared to A6, the A7 SoC no longer services the accelerometer, gyroscope and compass. To reduce power consumption, these functionalities have been moved to the new M7 motion coprocessor, a separate ARM-based microcontroller from NXP Semiconductors. 16

17 Apple A8 System-on-Chip Apple A8 is a 64-bit ARM-based SoC was introduced on Sept for the iphone 6 and iphone 6 Plus Apple states that it has 25% more CPU performance and 50% more graphics performance with 50% of the power compared to its predecessor A7. The A8 features the second generation of the Apple-designed 64-bit 1.4 GHz ARMv8-A dual-core CPU, called Cyclone Gen 2, and an integrated PowerVR Series 6XT GX6450 quad-core GPU. The A8 is manufactured on a 20 nm process by TSMC which replaced Samsung as manufacturer of Apple's mobile device processors. It contains 2 billion transistors. It has 1 GB of LPDDR3 RAM included in the package. On October 16, 2014, Apple introduced a variant of the A8, the A8X, in the ipad Air 2 with improved graphics and CPU performance due to one extra core and higher frequency 17

18 Moore s Law (1965): The numbers of transistors on a processor will double every 18 to 24 months Cristina Silvano Politecnico di Milano

19 The end of the historic scaling Chip density is continuing increase ~2x every 2 years Max Clock Frequency Wall Power Wall Expose parallelism in a coarser level than single thread Cristina Silvano Politecnico di Milano -19- March 2012

20 Stopper: On-Chip Temperature Wall Cristina Silvano Politecnico di Milano

21 Paradigm shift : Multi-core architectures ARM nm 11.8 mm nm, 5.2 mm 2 90 nm, 2.6 mm 2 65 nm 1.4 mm 2 Source: STMicroelectronics

22 Intel 80 core Cristina Silvano Politecnico di Milano

23 NVIDIA Fermi GPU Cristina Silvano Politecnico di Milano

24 NVIDIA Kepler GPU Kepler GK110 Architecture 7.1B Transistors 15 SMX units (2880 cores) >1TFLOP FP64 1.5MB L2 Cache 384-bit GDDR5 PCI Express Gen3 Cristina Silvano Politecnico di Milano

25 ACA COURSE INFORMATION Cristina Silvano Politecnico di Milano -25- March 2012

26 ACA Course Schedule Schedule: Second Semester (Spring 2015) Monday Location: D03 Leonardo Campus Wednesday Location: EG2 Leonardo Campus Cristina Silvano Politecnico di Milano

27 Contact Information Office hours for students: Tuesday at DEIB, Via Ponzio 34/5 First floor Internal phone number: 3692 (please send an to get an appointment). Main Contact: The students can contact prof. Cristina Silvano by by indicating: Subject: ACA COURSE Milano, Your_Surname, Your_Name, Your_POLIMI_ID_NUMBER Cristina Silvano Politecnico di Milano

28 ACA Teaching Assistants Prof. Giovanni Agosta Prof. Gerardo Pelosi Cristina Silvano Politecnico di Milano

29 ACA Course Info Teaching Activity: The course consists of 5 CFU and it is organized in 30 hours of lectures and 20 hours of written/tool-based exercises to prove the concepts presented during the lectures. Pre-requirements: Basic concepts on logic design and computer architectures. Cristina Silvano Politecnico di Milano

30 ACA Final Exam FINAL EXAM: The final exam consists of a written exam. For each written exam, a max. score of 32 points will be assigned to 6 questions: max. 16 points will be assigned for the solution of the exercise part (composed of 3 questions) and max. 16 points will be assigned for answering to the theory part (composed of 3 questions) It is possible to ask an OPTIONAL project to the instructor. The project must be concluded before each written exam session (firm deadline). The project assign an additional score up to max 12 points. The additional points given by the project will be added to the score of the written exam only if the final score of the written exam will be sufficient (>=18 points). The max 12 points assigned by the project can be used to avoid 2 out of 6 questions of the written exam Cristina Silvano Politecnico di Milano

31 ACA Teaching Material Additional information in slides and papers available through the course webpage: If you're using MOZILLA FIREFOX AS WEB BROWSER, for a correct visualisation and printing of the PDF SLIDES, please use the SAVE AS option and save the PDF FILE on your laptop for correct visualisation and printing. Reference Book: "Computer Architecture, A Quantitative Approach", John Hennessy, David Patterson, Morgan Kaufmann, Fourth Edition / Fifth Edition Cristina Silvano Politecnico di Milano

32 ACA Course ACA course is offered in English Teaching materials (slides/papers/textbook) are available in English Final exam can be done in English Teaching support available in English and Italian Please notice international students can follow the course HPPS (High Performance Processors and System) together with the ACA course session held by prof. Donatella Sciuto during the Second Semester ACA course objective and program are aligned with HPPS course. Final exam will be carried out separately. Cristina Silvano Politecnico di Milano -32- March 2013

33 Overview of the ACA topics How to increase performance while decrease the design cost? RISC: Reduced Instruction Set Computer Pipeline Can we gain more? Branch prediction Instruction Level Parallelism (ILP) Multithreading Multiprocessors Still performance does not scale? Memory hierarchy Cache organization Cristina Silvano Politecnico di Milano

34 Main lectures topics (1) Review of basic computer architecture definitions and components (Central Processing Unit, Memory System, Input/Output Interfaces, Communication System) Basic performance evaluation metrics of computer architectures Memory hierarchy: Basic and advanced concepts. Multi-level caches. Performance evaluation, optimisation techniques. Central Processing Unit: the RISC approach (Reduced Instruction Set Computer). Cristina Silvano Politecnico di Milano

35 Main lectures topics (2) Techniques for performance optimization: Pipelining: The problem of hazards: structural, control and data hazards; Optimization techniques to solve the problem of hazards Branch prediction techniques: Static and dynamic branch prediction techniques Speculative execution Cristina Silvano Politecnico di Milano

36 Sequential vs. Pipelining Instruction Execution I1 I2 IF ID EX MEM WB IF ID EX MEM WB 10 ns 10 ns Cristina Silvano Politecnico di Milano

37 Main lectures topics (3) Instruction Level Parallelism (ILP): Static and dynamic scheduling; Superscalar architectures; VLIW (Very Long Instruction Word) architectures; Cristina Silvano Politecnico di Milano

38 Instruction Level Parallelism: Example of 2-issue processor I1 I 1 IF ID EX MEM WB Time I2 I3 I4 I 2 IF 2 ns ID IF IF EX ID ID MEM EX EX WB MEM MEM WB WB Instruction Per Clock = 2 CPI = Clock Per Instruction = 0.5 I5 2 ns IF ID EX MEM WB I6 IF ID EX MEM WB I7 2 ns IF ID EX MEM WB I8 IF ID EX MEM WB I9 I10 2 ns IF IF ID ID EX EX MEM MEM WB WB Cristina Silvano Politecnico di Milano

39 Beyond ILP: Multithreading Threads: Independent sequences of instructions Single-threaded program Multi-threaded program

40 Main lectures topics (4) Beyond ILP: Multithreading (Thread Level Parallelism TLP) Multiprocessors and multicore systems: taxonomy, topologies, communication management, memory management, cache coherency protocols, example of architectures System-on-Chip and Network-on-Chip architectures; Digital Signal Processors; Stream processors and vector processors; Graphic Processors Cristina Silvano Politecnico di Milano