2000 N + N <100N. When is: Find m to minimize: (N) m. N log 2 C 1. m + C 3 + C 2. ESE534: Computer Organization. Previously. Today.

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1 ESE534: Computer Organization Previously Day 5: February 1, 2010 Memories Arithmetic: addition, subtraction Reuse: pipelining bit-serial (vectorization) shared datapath elements FSMDs Area/Time Tradeoffs Latency and Throughput 1 2 Today Preclass 1 Memory features When is: area/delay intuition and modeling design technology < Preclass 2 Preclass 2 Find m to minimize: Related? log 2 () m + C 2 m + C 3 5 log 2 () m + C 2 m + C 3 6 1

2 Delay Scale with bd? Scale with bw? Preclass 3, 4 What s a memory? Memory What s special about a memory? 7 8 Memory Function Memory Typical: Data Input Bus Data Output Bus Address (location or name) read/write control Block for storing data for later retrieval State element What s different between a memory and a collection of registers like we ve been discussing? 9 10 Collection of Registers Memory Uniqueness Cost Compact state element Packs data very tightly At the expense of sequentializing access Example of Area-Time tradeoff and a key enabler

3 Memory Organization SRAM Memory bit Key idea: sharing factor out common components among state elements can have big elements if amortize costs state element unique small 13 Source: 14 Memory Organization Share Interconnect Share: Interconnect Input bus Output bus Control routing very topology/wire cost aware design ote: local, abuttment wiring Input Sharing wiring drivers Output Sharing wiring sensing driving Address/Control Memory Organization Addressing and Control an overhead paid to allow this sharing

4 Dynamic RAM Goes a step further Share refresh/restoration logic as well Minimal storage is a capacitor Feature DRAM process is ability to make capacitors efficiently Some umbers (memory) Unit of area = λ 2 [more next week] (F=2λ) Register as stand-alone element 4Kλ 2 e.g. as needed/used last lecture Static RAM cell 1Kλ 2 SRAM Memory (single ported) Dynamic RAM cell (DRAM process) 100λ 2 Dynamic RAM cell (SRAM process) 300λ DRAM Layout DRAM Latency wordline bitline 21 Source: Performance 1000! 100! 10! 1! Moore s Law 1980! 1981! 1982! 1983! 1984! 1985! 1986! 1987! 1988! 1989! 1990! 1991! 1992! 1993! 1994! 1995! 1996! 1997! 1998! 1999! 2000! Time µproc 60%/yr. Processor-Memory Performance Gap: (grows 50% / year) DRAM DRAM 7%/yr. 22 Penn [From ESE534 Spring2010 Patterson -- DeHon et al., IRAM: CPU! Contemporary DRAM Memory Access Timing 1GB DDR3 SDRAM from Micron 96 pin pakage 16b datapath IO Operate at 500+MHz 37.5ns random access latency RAS/CAS access Optimization for access within a row

5 Contemporary DRAM 1 Gigabit DDR2 SDRAM 1GB DDR3 SDRAM from Micron 96 pin pakage 16b datapath IO Operate at 500+MHz 37.5ns random access latency 25 [Source: 26 Contemporary DRAM DRAM Latency 4GB DDR3 SDRAM from Micron modules/ddr3/ksf16c256_512x64hz.pdf Operate at 800MHz 50ns random access latency 27 Performance 1000! 100! 10! 1! Moore s Law 1980! 1981! 1982! 1983! 1984! 1985! 1986! 1987! 1988! 1989! 1990! 1991! 1992! 1993! 1994! 1995! 1996! 1997! 1998! 1999! 2000! Time µproc 60%/yr. Processor-Memory Performance Gap: (grows 50% / year) DRAM DRAM 7%/yr. 28 Penn [From ESE534 Spring2010 Patterson -- DeHon et al., IRAM: CPU! Basic Memory Design Space Width Depth Internal vs. External Width Banking To come What happens as make deeper? Depth

6 Banking Independent Bank Access Tile Banks/memory blocks Memory Key Idea Memories hold state compactly Do so by minimizing key state storage and amortizing rest of structure across large array Yesterday vs. Today (Memory Technology) What s changed? Yesterday vs. Today (Memory Technology) What s changed? Capacity single chip Integration memory and logic dram and logic embedded memories Room on chip for big memories And many memories Don t have to make a chip crossing to get to memory 35 Important Technology Cost IO between chips << IO on chip pad spacing area vs. perimeter (4s vs. s 2 ) wiring technology BIG factor in multi-chip system designs Memories nice very efficient with IO cost vs. internal area 36 6

7 On-Chip vs. Off-Chip BW Costs Change Use Micron 1Gb DRAM as example On Chip BW: assume b banks? assume b banks? assume b banks? 37 Design space changes when whole system goes on single chip Can afford wider busses more banks memory tailored to application/architecture Beware of old (stale) answers their cost model was different 38 What is Importance of Memory? Radical Hypothesis: Memory is simply a very efficient organization which allows us to store data compactly (at least, in the technologies we ve seen to date) A great engineering trick to optimize resources Alternative: memory is a primary State is a primary, but state memory 39 Admin Added paper on modeling memories as supplemental reading for today Reading for next Monday on web Classic paper on MOS scaling Reading for next Wednesday in Blackboard 40 Big Ideas [MSB Ideas] Memory: efficient way to hold state Resource sharing: key trick to reduce area Memories are a great example of resource sharing Big Ideas [MSB-1 Ideas] Tradeoffs in memory organization Changing cost of memory organization as we go to on-chip, embedded memories

8 log 2 () m Related? m=bw bw*bd= So bd=/m Preclass 2 + C 2 m + C 3 Preclass 2 bd log 2 () + C 2 bw + C 3 C 3 is for area of single memory cell log 2 (n) is for decoder In red is for gates in decoder 43 C 2 is for amps at bottom of row and drivers at top 44 Preclass 1 log 2 () m + C 2 m + C 3 When we solved for, we found m is proportional to log 2 () + C 2 + C 3 If we approximate log 2 () as a constant, we get C 4 + C