Module 3.C. Serial Peripheral Interface (SPI) Tim Rogers 2017

Transcription

1 Module 3.C Serial Peripheral Interface (SPI) Tim Rogers 2017

2 Learning Outcome #3 An ability to effectively utilize the wide variety of peripherals integrated into a contemporary microcontroller How? A: Clocks and Real Time Interrupt (RTI) B: Analog-to-Digital Converter (ATD) C: Serial Peripheral Interface (SPI) D: Timer Module (TIM) E: Pulse Width Modulation (PWM) F: Serial Communications Interface (SCI) [3.B]-2

3 Learning Outcome #3 One options: Send data in parallel Serial Peripheral Interface (SPI) Why? Want to communicate with a peripheral Better option: Send multi-bit data serially Port X.7. Port Y.2 IRQ Printer STROBE BUSY.. Port Y.3 Port X.0 1 Port Y.1 CLR D Q Q where Port X and Port Y are any available port pins CLK Data [3.B]-3

4 Basic Description Communication takes place serially Synchronous because a clock signal is involved Operates in Master/Slave Mode. Needs to be one master can be multiple slaves Master defines the clock Operates via shifting in bits each clock cycle Standardized and used for a variety of peripherals: LCDs, D/A converters, etc Can also use it to communicate between microcontrollers [3.B]-4

5 Basic SPI Operation Master owns the clock MASTER SLAVE MOSI Master Out, Slave In MISO Master In, Slave Out [3.B]-5

6 9S12 SPI Module Full-Duplex Can manipulate SPI clock Can be program or interrupt-driven. [3.B]-6

7 SPI Block Diagram PM.4 PM.2 PM.5 Port M 24 MHz PM.3 7

8 SPI Registers SPICR1 (SPI control register 1) SPIE (bit 7) 0 SPI interrupts disabled 1 SPI interrupts enabled SPE (bit 6) 0 SPI system disabled 1 SPI system enabled SPTIE (bit 5) 0 SPTEF (transmit empty) interrupt disabled 1 SPTEF (transmit empty) interrupt enabled indicates default mode after RESET 8

9 SPI Registers SPICR1 (SPI control register 1) MSTR (bit 4) 0 slave mode enabled 1 master mode enabled CPOL (bit 3) 0 active high clock (SCK low in idle state) 1 active low clock (SCK high in idle state) CPHA (bit 2) 0 data sampling occurs at odd edges of SCK 1 data sampling occurs at even edges of SCK indicates default mode after RESET 9

10 SPI Clock Format with CPOL=0, CPHA=0 10

11 SPI Registers SPICR1 (SPI control register 1) SSOE (bit 1) 0 slave select output disabled 1 slave select output enabled (in master mode, provided MODFEN bit is also 1 ) LSBFE (bit 0) 0 data transferred most significant bit first 1 data transferred least significant bit first indicates default mode after RESET 11

12 SPI Registers SPICR2 (SPI control register 2) BIDIROE (bit 3) MOSI/MISO output enable in bi-directional mode 0 output buffer disabled 1 output buffer enabled SPC0 (bit 0) serial pin control bit 0 bi-directional mode is disabled 1 bi-directional mode enabled indicates default mode after RESET 12

13 SPI Modes Master Key: Master Slave Input Output 13

14 SPI Registers SPIBR (baud rate) SPRx (bits 2-0) baud rate preselection bits SPPRx (bits 6-4) baud rate selection bits BaudRateDivisor = (SPPR + 1) 2 (SPR + 1) BaudRate = BusClock / BaudRateDivisor Example: If SPR=000 and SPPR=000 (default), then BaudRateDivisor = 2 BaudRate = BusClock/2 14

15 SPI Registers SPISR (status) SPIF (bit 7) set after a received data byte is copied into the SPI data register 0 transfer not yet complete 1 received data copied to SPIDR Cleared by reading SPISR (status) register followed by reading SPIDR (data) register SPTEF (bit 5) set when the transmit data register is empty 0 SPI transmit data register not empty 1 SPI transmit data register is empty indicates default mode after RESET 15

16 SPI Registers SPIDR (data register) serves as both the input and the output data register for the SPI PORTM (Port M data register) MISO (bit 2) SS (bit 3) MOSI (bit 4) SCK (bit 5) 16

17 1. The synchronous aspect of an SPI interface means: A. data can only be transmitted in one direction B. data can be transmitted in both directions, but not at the same time C. data can be transmitted in both directions simultaneously D. data transmission requires a clock signal E. none of the above 17

18 2. The minimum SPI baud rate divisor possible is: A. 1 B. 2 C. 4 D. 8 E. none of the above 18

19 3. Based on a 24 MHz system clock, the maximum SPI data transfer rate possible (in bits/second) is: A. 2,000,000 bps B. 4,000,000 bps C. 8,000,000 bps D. 12,000,000 bps E. none of the above 19

20 4. The maximum SPI baud rate divisor possible is: A. 128 B. 896 C D E. none of the above 20

21 5. Based on a 24 MHz system clock, the minimum SPI data transfer rate possible (in bits/second) is approximately: A. 8,000 bps B. 11,719 bps C. 93,750 bps D. 1,500,000 bps E. none of the above 21

22 SPI Initialization Code ; Select 1.5 Mbps baud rate (24 MHz bus) spini movb #$12,spibr [3.B]-22

23 SPI Registers SPIBR (baud rate) SPRx (bits 2-0) baud rate preselection bits = 010 SPPRx (bits(6-4) baud rate selection bits = 001 BaudRateDivisior = (1 + 1) 2 (2 + 1) = 16 BaudRate = 24 MHz / 16 = 1.5 Mbps SPIBR = x 001 x 010 = $12 23

24 SPI Initialization Code ; Select 1.5 Mbps baud rate (24 MHz bus) spini movb #$12,spibr ; Master mode, Interrupts off, CPOL=0, ; CPHA=0, slave select disabled, data ; transferred most significant bit first movb #$50,spicr1 [3.B]-24

25 SPI Registers SPICR1 (SPI control register 1) SPIE (bit 7) 0 SPI interrupts disabled 1 SPI interrupts enabled SPE (bit 6) 0 SPI system disabled 1 SPI system enabled SPTIE (bit 5) 0 SPTEF interrupt disabled 1 SPTEF interrupt enabled indicates default mode after RESET 25

26 SPI Registers SPICR1 (SPI control register 1) MSTR (bit 4) 0 slave mode enabled 1 master mode enabled CPOL (bit 3) 0 active high clock (SCK low in idle state) 1 active low clock (SCK high in idle state) CPHA (bit 2) 0 data sampling occurs at odd edges of SCK 1 data sampling occurs at even edges of SCK indicates default mode after RESET 26

27 SPI Registers SPICR1 (SPI control register 1) SSOE (bit 1) 0 slave select output disabled 1 slave select output enabled (in master mode, provided MODFEN bit is also 1 ) LSBFE (bit 0) 0 data transferred most significant bit first 1 data transferred least significant bit first indicates default mode after RESET 27

28 SPI Initialization Code ; Select 1.5 Mbps baud rate (24 MHz bus) spini movb #$12,spibr ; Master mode, Interrupts off, CPOL=0, ; CPHA=0, slave select disabled, data ; transferred most significant bit first movb #$50,spicr1 ; Normal (non-bidirectional) mode clr spicr2 rts [3.B]-28

29 SPI Registers SPICR2 (SPI control register 2) BIDIROE (bit 3) MOSI/MISO output enable in bi-directional mode 0 output buffer disabled 1 output buffer enabled SPC0 (bit 0) serial pin control bit 0 bi-directional mode is disabled 1 bi-directional mode enabled indicates default mode after RESET 29

30 SPI transmit/receive code ;Transmit data passed in A register ;Return data read in B register ;Transmit - wait for SPTEF to set spio brclr spisr,$20,spio staa spidr ;transmit data ;Receive - wait for SPIF to set sprlp brclr spisr,$80,sprlp ldab spidr ;read data rts [3.B]-30

31 SPI Registers SPISR (status) SPIF (bit 7) set after a received data byte is copied into the SPI data register 0 transfer not yet complete 1 received data copied to SPIDR Cleared by reading SPISR (status) register followed by reading SPIDR (data) register SPTEF (bit 5) set when the transmit data register is empty 0 SPI transmit data register not empty 1 SPI transmit data register is empty indicates default mode after RESET 31

32 SPI Application Multiple I/O Devices 32

33 SPI Application 8-bit Shift Register/ Constant Current LED Driver MOSI SCLK MISO (optional) GPIO GPIO 33

34 SPI Application External 12-bit ATD 34

35 SPI Application External 8/10/12-bit DTA 35