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1 STM32F3 Technical Training For reference only Refer to the latest documents for details
2 Serial peripheral interface SPI
3 3 SPI Features (1/2) 3 Full duplex synchronous transfers (3 lines) Half duplex/simplex synchronous transfers (2 lines, bi-directional data line at half duplex) Programmable clock polarity & phase, data MSB/LSB first Master/multi Master/Slave operation Dynamic software/hardware NSS management (Master/Slave) Hardware CRC feature (8-bit & 16-bit data frames checking) Flags with IT capability (TxE, RxNE, MODF, OVR, CRCERR) Programmable bit rate: up to f PCLK /2 BSY flag (ongoing communication check) DMA capability (separated Rx/Tx channels, automatic CRC & Tx/Rx access/threshold handling) Up to 18 MHz bit rate
4 4 SPI Features (2/2) 4 NEW! New enhanced NSS control: NSS pulse mode (NSSP) TI mode Programmable data frame from 4-bit to 16-bit Two 32-bit Tx/Rx FIFO buffers with DMA capability Data packed mode control
5 5 SPI block scheme 5 (SD) (MCLK) (CK) (WS)
6 6 Data Frame Format (Motorola mode) 6 Data frame format : Programmable size of transfer data frame format from 4-bit up to 16-bit Programmable clock polarity & phase, data bit order MSB/LSB first
7 7 NSS management 7 NSS input SSM selects HW control (NSS pin) or SW control (SSI bit): Slave mode - select slave for communication (optionally can be used for synchronization of a transaction begin) Master mode - signalize conflict between masters NSS output HW control at master mode only (SSM=0, SSOE=1 or at specific modes - TI, NSSP)
8 8 Communication modes 1/3 Full Duplex mode (Single master & single slave) Three lines are necessary at least - MISO, MOSI, SCK (NSS is optional) 8 Up to 16-bit shift register MISO MISO Up to 16-bit shift register MOSI MOSI Clock generator SCK SCK Master NSS NSS Slave NSS NSS NSS HW management NSS SW management
9 9 Communication modes 2/3 9 Simplex mode (Single master & single slave) Two lines are necessary at least (NSS is optional): MISO & SCK (Master Rx only, Slave Tx only) MOSI & SCK (Master Tx only, Slave Rx only - at below figure) Up to 16-bit shift register! MISO MISO Up to 16-bit shift register MOSI MOSI Clock generator SCK SCK Master NSS NSS Slave
10 Communication modes 3/3 10 Half duplex mode (Single master & single slave) Two lines are necessary at least - bidirectional cross data line MOSI- MISO and SCK (NSS is optional) Up to 16-bit shift register MISO MISO Up to 16-bit shift register MOSI MOSI Clock generator SCK SCK Master NSS NSS Slave
11 11 Multi slave system (duplex/simplex) 11 Up to 16-bit shift register Clock generator Master MISO MOSI SCK GPIO MISO MOSI SCK NSS! Up to 16-bit shift register Slave Separated NSSs At full duplex one slave only (just selected by NSS) can communicate with master at time Master GPIO GPIO MISO MOSI SCK NSS! Up to 16-bit shift register Slave Common NSS Slaves at simplex Rx only mode can receive the same data sent in parallel from master To next slaves MISO pin can t be used at this case
12 Multi slave circular duplex chain 12 Data lines are connected into a closed loop Master must shift the data through all of the slaves One common NSS is used
13 Two separated 32-bit FIFOs for receive and transmission 32-bit Rx and Tx FIFOs 13 8-bit or 16-bit read/write access to FIFOs. Occupancy level flags FTLVL[1:0], FRLVL[1:0], TxE, RxNE Different capability of Tx and Rx FIFOs
14 Packed mode & FIFOs access 14 When data frame fits into one byte (from 4 up to 8 bits) two patterns can be accessed in parallel by single write/read FIFOs. Example: 4-bit data frame length, MSB first, 16-bit threshold is set for RxFIFO, both FIFOs can be accessed by single 16-bit read or write 1x TxE event at transmitter - 1x RxNE event at receiver
15 DMA 15 DMA handles automatically: all the TXE and RXNE events CRC is sent after last data frame Initialization of CRC calculation change of data register access and Rx threshold control of the last data frame in case it is an odd frame at packed mode (user must set LDMA_TX & LDMA_RX bits at this case!) Packed mode is used by DMA: data frame fits into one byte when peripheral size (PSIZE) is set to 16-bit for SPI DMA channel Notes: OVR flag is set at transmit only mode (SPI continues to receive) BSY & FTLVL must be checked before SPI is disabled
16 BSY flag 16 Communication activity checking (to prevent corruption of ongoing transfer) Before SPI or its clock are disabled (at some modes) Before entry to Halt Cleared under any one of the following conditions: When the SPI is properly disabled When a master mode fault occurs (MODF=1) In master mode between transactions when no next pattern is ready to transfer (FTLVL=00) In slave mode between each data pattern transfer Note: BSY & FTLVL must be checked before SPI is disabled
17 17 CRC calculation (1/3) 17 Hardware CRC feature for reliable communication: Separated CRC calculators implemented for transmitted and received data CRC value is transmitted as a last transaction(s) CRC error checking for last received byte and interrupt generation on error Programmable CRC polynomial calculation (odd polynomials only) Available for 8-bit or 16-bit data patterns only Two possible CRC calculations: CRC8, CRC16-CCITT standard
18 18 CRC calculation (2/3) 18 Example of n data transfer between two SPIs followed by the CRC transmission of each one in Full-duplex mode SPI_TXCRCR and SPI_RXCRCR separated registers for CRC calculation MOSI Data 1 Data 2 Data n CRC[1..n] Transmitter puts calculated CRCNXT=1 CRC value into TxFIFO Receiver - compares last frame(s) MISO Data 1 Data 2 Data n CRC [1..n] at RxFIFO with calculated CRC SCK CRCERR interrupt NSS
19 R = 4.7 KΩ 19 CRC calculation (3/3) 19 Basic SD/MMC support (SPI protocol): Performance: speed up to 18MHz Error checking: hardware CRC calculation V DD V DD Master MISO SCK MOSI CS
20 Pulse mode (NSSP=1) NSS enhanced modes (1/2) 20 At master and Motorola mode with CPHA=0 only NSS output is managed by HW
21 TI mode (FRF=1) NSS enhanced modes (2/2) 21 Clock and NSS are managed by HW At slave, baud rate setting defines trelease (MISOs HiZ) Format frame error interrupt (FRE)
22 When data packed mode is used Be careful! Keep Rx threshold & read access of Rx FIFO always in line either 8-bit or 16-bit (preferable -> limited number of events) Change Rx threshold just before last odd data frame is received 22 When go to Halt or when disable the SPI check read FIFO occupancy and bus activity (FxLVL[1:0] = 00 & BSY = 0) When communication is continuous (e.g. master Rx-only) Perform Rx threshold, change/crc control or Stop within Control window CRCNXT=1 RXONLY=0 FRXTH=1 Dummy/Odd/CRC Frame CPHA=0 Control window
23 What is a maximum SPI speed? When data packed mode is used? What should be in line when access the RxFIFO? Quiz 23 Does a master take any care of the NSS signal level if it is managed by SW? How many bytes (maximum) can be stored into TxFIFO till it is full when 8-bit access is used? What should precede before SPI is disabled?
24 24
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