Board Design Best Practices

Transcription

1 June 26, 2007 Board Design Best Practices AZ310 John Weil Systems and Applications Engineering Manager

2 Session Objectives Following this session, you will be able to: Provide a board design check list. Describe best practices for hardware design when using ColdFire processors. Identify and provide access to collateral and other support resources for the product. 1

3 Introductions Instructor: John Weil 32-Bit Applications / Systems Manager Have done hardware design for the last 12+ years Did 4 years of industrial controls Designed conveyors & robotic systems for factory automation. PLC programming & electrical system design etc Worked as Freescale FSRAM (Fast-Static RAM) test engineer doing high speed board design Have spent the last 7 years or so doing systems engineer work. Designed imaging solutions for customers USB, Ethernet, DDR, PCI, and many other standards 2

4 Objectives for this Training Session Establish a baseline for designing a low end V2 class ColdFire solution. Using M5282 EVB Schematics as a baseline Discuss some of the interesting things that we did and that customers may want to implement on their designs. Discuss common mistakes in board design Are there areas for improvement? What should you watch for when reviewing a customer design? Review common ColdFire design requirements and briefly discuss reasons for some requirements. Provide low end V2 Microcontroller layout example and considerations (MCF5213) Discuss Freescale s latest V4e products (547x and 548x) and what special board design considerations need to be made. Clocking DDR interface FlexBus interface PCI USB 3

5 MCF5282 Overview 68K/ColdFire V2 Core Up to 76 Dhrystone MHz Enhanced MAC Module and HW Divide Integration 2K bytes I/D-Cache 64K bytes SRAM Up to 512K bytes Flash 100K W/E cycles, 10 years data retention 10/100 Ethernet MAC (external PHY) CAN 2.0B Controller (FlexCAN) 3 UARTs (2 with flow control) Queued Serial Peripheral Interface (QSPI) I 2 C bus interface 4 ch. 32-bit timers with DMA support 8 ch. 16-Bit Capture/Compare/PWM timers 4 ch. Periodic Interrupt Timer 8 ch. Queued 10-bit A-to-D converter 4 ch. DMA controller SDRAM Controller 32-bit non-multiplexed data bus with 7 Chip Selects Up to 150 General-Purpose I/O System Integration (PLL, SW Watchdog) Single 3.3V supply / 5V tolerant I/O Availability Offered at -40 C to MHz and 80MHz Package: 256-ball MAPBGA BDM 4ch 32-bit Timer 8ch 16-bit Timer 4ch PIT 512KBytes Flash EMAC PLL 4ch DMA QSPI I 2 C V2 ColdFire Core 2K I/D Cache GPI/O UART UART UART System Bus Controller 64K SRAM JTAG 10/100 FEC CAN DMA 8ch 10-bit QADC SDRAM Controller & Chip Selects 4

6 ColdFire Board Design Using M5282EVB Schematics Page 1: Hierarchical Overview Not much here, just a high level view of how everything connects together. Terminology Summary for the schematics. These are commonly used reference designators, that you will find on our boards and customer boards. C = Capacitor ex: C1 D = LED ex: D1 J = Connecter (male) ex: J1 P = Plug (female) ex: P1 R = Resistor ex: R1 T = Transformer ex: T1 U = Device ex: U1 Y = Crystal ex: Y1 RP = Resistor pack ex: RP1 SW = Switch ex: SW1 TP = Test point ex: TP1 5

7 ColdFire Board Design Using M5282EVB Schematics Page 2: CAN Transceiver Connector R2 is the loopback load resistor and it represents the impedance of the system JP1 places transceiver into standby mode. 6

8 ColdFire Board Design Using M5282EVB Schematics Page 3: MCF5282 (Network ready MCU) 256 ball MAPBGA When designing boards with large numbers of I/Os, try to group signals together according to their function. (i.e. DATA, ADDRESS, control, etc ) This makes for easier review at a later date. Usage of bypass capacitors is recommend. Note: A key Rule of Thumb implemented on this EVB is that for capacitors of less than 0.1uF value a dielectric material of either COG or NPO should be used. This dielectric material is more self resonant than X7R material for example and so will absorb a lot more EMC noise at the capacitors self resonant frequencies. In this case the values of the by-pass/decoupling capacitors are chosen such that the fundamental and 3rd, 5th & 7th harmonic frequencies of the CPU core will be absorbed. All capacitors greater than or equal to 0.1 uf should be X7R material. Body type for capacitors is In general I use low ESL/ESR caps. Smaller the footprint, the better, because it typically lowers the overall inductance between the system and the cap. Emulation Technology Sockets are used on this board. Emulation Technology sockets are good general purposes sockets for customer development. These sockets can typically solder down using the same part footprint. Electrical performance is typically good enough for ColdFire parts. The one exception to using this sort of socket, would be when doing USB 2.0 HS work with our higher end ColdFire products. A low impedance socket must be used if signal quality is an issue for the customer. The ET socket is good enough to do development with our parts. 7

9 ColdFire Board Design Using M5282EVB Schematics Page 3: MCF5282 (Network ready MCU) 256 ball MAPBGA PLL filtering and layout are critical to provide the most stable Vdd as possible to the MCF5282 PLL internal circuitry. Please review the filtering components that connect to pin N8 of the MCF5282. The placement of the R and C(s) is very important. If your customer will allow passive components on the backside of the board, then place components as close to the N8 via as you can (assuming BGA vias are not blind and buried). If back side components are a problem, then place components as close to the ColdFire package as you can, on the same side at the N8 BGA location. 8

10 ColdFire Board Design Using M5282EVB Schematics Page 3: MCF5282 (Network ready MCU) 256 ball MAPBGA There are two resistor packs, which are used on the SDRAM control signals for series termination of the uni-directional signals from the MCF5282 to the DRAM memories. Series termination of the SDRAM control signals with 22 Ohm Rpacks, will minimize overshoot and undershoot on these critical signals. Keep in mind that when doing series termination, it is most affective when placed close to the source driver. Placing a series terminator somewhere in the middle of a long trace, will have negative affects. This is why series terminators are sometimes located on the same page as the source I/O driver. Series termination is commonly used to match I/O driver impedance to trace impedance. The 22ohm series terminator is a common size and will generally work as a good starting point for reducing unwanted ringing (overshoot/undershoot). Proper selection of series terminators can be determined by comparing output impedance of I/O driver, with trace impedance. The usage of IBIS models is typically the preferred method to calculate this. 9

11 ColdFire Board Design Using M5282EVB Schematics Page 4: Ethernet 10/100 Ethernet physical interfaces can be broken down into a transceiver and an isolation transformer (magnetics). The transceiver communicates with the MAC over a simple digital bus call MII (Media Independent Interface). Most E-phys require a 25Mhz Clock source. The MII interface transmits and receives (full-duplex mode) 4-bits of data (nibble) on each 25Mhz clock edge. This gives the fastest transfer rate of 100Mbps. The magnetics provide the needed isolation from the cable to the sensitive pins on the transceiver. In general many different vendors supply good E-Phys, please follow each vendors implementation guide closely, as the quality of your ethernet connection is many times dependent on board routing, magnetics quality, and the configured mode of operation for the E-Phy. 10

12 ColdFire Board Design Using M5282EVB Schematics Page 5: Expansion Connectors Basic expansion connector with a wide variety of commonly needed signals, that are made available for daughter card use. Some of our ColdFire product boards have these two 120-pin connectors that are available for customers to plug-in a daughter card. Signals are not buffered There are reference designs for the design of daughter cards on our website. 11

13 ColdFire Board Design Using M5282EVB Schematics Page 6: Flash Memory Our board designs contain flash memory, that is available to store boot code. This board design uses an AMD flash, which stores our dbug ROM Monitor code. This flash can be reimaged using debug tools through the ColdFire BDM interface or using the dbug code. Chip select: (~CS0) is a special chip select that acts as a global chip select when the MCU comes out of reset. All external bus cycles are address decoded to the global chip select, until CS0 s valid bit is set in its CSMR register. Once this valid bit is configured, then CS0 will only respond to its programmed address range. The ColdFire external interface module is capable of a glueless interface to typical flash memory devices. I want to point out byte and address significance on this class product. Reminder that ColdFire A0 corresponds to Data[31:24] and when using a 16 bit flash, the customer need only connect ColdFire addresses A1 and higher. Simple concept, but remember that flash memory A0 is sized to data bus width, which is 16 bits in this case. ColdFire A0 is sized to its smallest addressable size, which is a byte. Remember that the ColdFire family uses a big endian architecture. 12

14 ColdFire Board Design Using M5282EVB Schematics Page 7: SRAM Memory Many of our board designs contain SRAM memory, that is available to store boot code or whatever the customer would like. Again A glue-less interface between ColdFire and SRAM. Please note the byte-lane order, address significance, and data bus bit ordering. DATA[31:0] BS[3:0] SRAM is a x36 (means it supports parity bits) but we only use 32 bits Since bus size is 32bits, we only need address A2 and higher. The SRAM s least significant addressable memory location will match up with ColdFire s 4 byte address (A2). One last comment On this design the designer decided to float the parity bits for each byte lane. This is typically a point of concern for our SRAM vendors. Please encourage your customers to tie parity bits to ground with a resistor. 13

15 ColdFire Board Design Using M5282EVB Schematics Page 8: BDM Port and Reset Config The BDM connector is extremely important for ColdFire based designs. For those that have PowerPC experience, this interface can be compared to the PowerPC COP debugger interface, in that both serve similar purposes. The BDM is very important because this port with the addition of a development tool (from Freescale or one of our third parties) will allow direct access to internal ColdFire registers, allow you to generate bus cycles to help debug your boards, allow you to program flash, and a whole host of additional debugging options. The BDM connector is defined by Freescale and we work with tool vendors to make sure their equipment is compatible with our pinout standard. Customers should follow a BDM pinout from one of our many Freescale EVBs. In summary the ColdFire BDM port helps customers reduce their design cycle time, when its enabled with a hardware/software development system. 14

16 ColdFire Board Design Using M5282EVB Schematics Page 8: BDM Port and Reset Config Many products in the ColdFire family depend on a reset configuration, to configure boot parameters and other out of reset parameters. In this example: The 5282 monitors a select group of signals while its input reset signal is asserted. Once this reset is de-asserted the configuration is latched internally and will not sample the external bus again without asserting reset. A buffer/transceiver as shown in the picture, can be used to isolate the pull-up and pull-down resistors from the external data bus. A careful load analysis, would allow customers to remove the buffer/transceiver and use direct pull-up and pull-downs. But customers should be aware that if strong pull-ups or pull-downs are used, then bus performance could be affected. 15

17 ColdFire Board Design Using M5282EVB Schematics Page 10: Power supplies and reset logic Customer should make sure to de-bounce any push buttons that can cause the MCU to have erratic behavior. Example: A user should always de-bounce the reset signals that are driven by mechanical push-buttons. There are a variety of ways to de-bounce a push button. The diagram shows an IC that provides a voltage sense reset and an input for a pushbutton reset. (A simple up Supervisor circuit.) This page also shows how to provide some isolation for analog power and ground planes. The addition of a relatively small inductor between your analog power to digital power planes will help prevent filter switching noise from affecting your analog power plane. The same concept will work on the ground planes as well. Remember that inductors in general will block AC and allow DC to pass. Sizing of inductor is system dependent and may have to be tuned per each customer application, because it will be dependent on the types of filtering that is already present on the digital power planes. 16

18 ColdFire Board Design Using M5282EVB Schematics Page 11: Pull-Ups and Test Points The ColdFire MCUs have several signals that customers should make sure they pull-up. When reviewing a customer design, this is a common place to find honest mistakes. It is easy to miss some of these signals. Chipselects should always have pull-ups. IRQ signals should have pull-ups, unless they are driven from digital logic like a FPGA or CPLD, which will guarantee an asserted or deasserted state. TA (Transfer Acknowledge) can cause customers a lot of grief if they forget about it. It must be pulled high and there is no way to disable this signal. ColdFire allows a bus cycle to be terminated early by asserting the TA signal (low). Some customers believe that if they program a waitstate count, then they don t have to worry about TA. Reset signals. Both RSTO (reset out) and RSTI (reset input) are active low signals, which need pull-ups. All active low bus control signals. This depends on the ColdFire part, but common signals are TSIZ, TEA, TS, OE, R/W#, and the BS (byte strobes or byte enables.) BDM connections (DSO, DSI, DSCLK, BKPT) 17

19 ColdFire Board Design Using M5282EVB Schematics Page 12: SDRAM The 5282 supports SDRAM on the same external bus interface that you connect the flash and other peripherals. Note that the byte strobes must be connected (BS[3:0]) and are connected to the SDRAM s data masks (sometimes called DMs or DQMs). The strobes must be connected to match the byte significance of the data bus. BS[3] D[31:24] BS[2] D[23:16] BS[1] D[15:8] BS[0] D[7:0] The toughest part of doing a SDRAM interface with the 5282, is understanding how to deal with the mux d bus required for SDRAMs. The 5282 user manual has tables that show example mux configurations. Using the SDRAM s datasheet and the 5282 s manual you should be able to route the ColdFire address lines to their proper locations. Keep in mind that 64-bit SDRAM DIMMs typically support two chipselects, which will let you address the upper and lower 32 bits using two chipselects. One chipselect for the lower 32 bits and one for the upper 32 bits. Watch the external bus loading very carefully. Since this bus is your local bus and your SDRAM bus, it is very easy to get into trouble with trace routing and overall capacitive load. 18

20 ColdFire Board Design Using M5282EVB Schematics Page 13: UARTs The transceivers are a must if you plan on connecting cables or any loads that might be off board. Simple serial communication between ASICs/SoCs do not typically require transceivers when chips are on the same board. There are many different RS232 drivers on the market. This circuit is very simple and can be re-used easily. 19

21 ColdFire V2 Sensor / Radio Low Cost Board Example Low cost Reference Design ColdFire MCF5213 and 3-axis accelerometer with ZigBee Radio connectivity. Very Small Form Factor Applications: 1. Shipping system data logger. Was shipping container harmed in anyway? 2. RF package tracking. 3. Interactive toys. (Wii like Game controls) Software Model: 1. USB connectivity through UART. 2. DSP filters that run real-time on 3- axis data from A/D converter. 3. Secure high speed flash allows for near real-time data logging at over 3khz sample rate. 20

22 Low End MCF5213 Microcontroller Layout Example Make it easy on yourself Use existing footprints available from our website Easily imported in to OrCAD Example of footprint on right No need for external crystal Use internal oscillator PLL fully functional Pull-up following signals XTAL CLKMOD[1:0] /RCON Pull-down EXTAL Always use pull-up/down Resistors on Clock Signals!! 21

23 Low End MCF5213 Microcontroller Layout Example Use Reduced BDM Header Save 16 pins on your board! RESET Switch and LED optional Uses ALLPST signal in place of PST[3:0] signals No ability to do real-time Trace Requires custom adapter to 26 pin P&E wiggler Add switch, jumper or other if planning to alternate between JTAG and BDM modes 22

24 Low End MCF5213 Microcontroller Layout Example Easily integrate sensors Below is an example of adding a Freescale XYZ accelerometer on A/D lines 23

25 Low End MCF5213 Microcontroller Layout Example Wireless Communication via Freescale s MC13192 ZigBee Transceiver and F antenna Must match impedance on antenna lines! 24

26 Objectives for this training session 2nd Hour Discuss Freescale s latest V4e products (547x and 548x) and what special board design considerations need to be made. Clocking DDR interface FlexBus interface PCI USB 25

27 68K/ColdFire V4e Core Up to 410 Dhrystone MHz MMU, FPU, EMAC Integration 32K bytes I-Cache, 32K bytes D-Cache 32K bytes SRAM Up to two 10/100 Ethernet MACs (external PHYs) Optional Hardware Accelerated Encryption Random Number Generator DES, 3DES, AES, Block Cipher Engine MD5, SHA-1, HMAC, Hash Accelerator Optional USB 2.0 high-speed device with integrated PHY Four Programmable Serial Controllers (PSC) UART, USART, IrDA and modem capability Queued Serial Peripheral Interface (QSPI) I 2 C bus interface 32-bit v2.2 PCI interface, 33/66 MHz, five external masters 4 ch. 32-bit timers with DMA support 4 ch. Periodic Interrupt Timer 4 ch. DMA controller SDRAM Controller Up to 99 General-Purpose I/O System Integration (PLL, SW Watchdog) 1.5V Core, 3.3V I/O Availability Temperature Range: 0ºC to 70ºC Package: 388 PBGA 2 nd 10/100 FEC Crypto USB device Optional Additional Modules EMAC BDM MMU MCF547x Overview 32K SRAM FPU PLL 4ch 32-bit Timer 16ch DMA 10/100 FEC V4e ColdFire Core 32K I-Cache PCI Controller GPI/O PSC (UxART etc.) DSPI I 2 C System Bus Controller 32K JTAG PSC (UxART etc.) PSC (UxART etc.) PSC (UxART etc.) D-Cache DDR/SDR SDRAM Controller 26

28 General Comments Designing for this Family When doing schematic capture on a high pin count device, I recommend using a heterogeneous symbol verses a homogeneous version. The MCF5282 schematics used a homogeneous symbol because of the low overall pin count. With the high pin count of the 547x and 548x I recommend segmenting your symbol into different functional blocks. It makes the schematics easier to read. The FlexBus clock and PCI clock are driven from the system board and not from the ColdFire MCU. Use zero-delay buffers when supporting multiple synchronous devices on the PCI bus. 27

29 Designing with DDR SDRAM The MCF547x and MCF548x are the first ColdFire products with a DDR memory interface. DDR stands for dual data rate. How is this different than SDRAM? DDR memories will drive data on the rising and falling edge of each clock cycle. The 547x and 8x take advantage of this by supporting a 32 bit DDR memory bus and a 64-bit internal data bus. Each external clock cycle delivers 64 bits of data to the internal bus. 28

30 Designing with DDR SDRAM The MCF547x and MCF548x are the first ColdFire products with a DDR memory interface. DDR stands for dual data rate. How is this different than SDRAM? DDR memories will drive data on the rising and falling edge of each clock cycle. The 547x and 8x take advantage of this by supporting a 32 bit DDR memory bus and a 64-bit internal data bus. Each external clock cycle delivers 64 bits of data to the internal bus but only needs 32 pins to do so. Write cycle timing: Note that the DQS signals (data strobes) are aligned such that the edge is centered in the data valid window. t SK t SK t CK t CKH t CKL MEMCLK0 MEMCLK1 t SK t SK t SK t SK MEMCLK0# MEMCLK1# t SK t SK CS#,WE#, RAS,CAS t CMV t CMH Command MEMADDR, BANK t CMV ROW t CMH COLUMN t QS t QH DM DQS t DQSS t QS t QH MEMDATA WD1 WD2 WD3 WD4 29

31 Designing with DDR SDRAM Read cycle timing: Note that the DQS signals (data strobes) are aligned such that the rising and falling edges surround the data valid window. This is important because the Freescale DDR controller has a true DQS block that adjusts for each byte lane. The DQS block delays the DQS edges by one ¼ clock and uses those edges to sample in the middle of the data valid window. The DQS module will automatically adjust for temp, voltage, and process variation and requires just a few system design considerations. t SK t SK t CK t CKH t CKL MEMCLK0 MEMCLK1 t SK t SK MEMCLK0# t SK t SK MEMCLK1# t SK t SK CS#,WE#, RAS,CAS t CMV t CMH Command MEMADDR, BANK t CMV ROW t CMH COL CL=2 DQS DQS Read Preamble DQS Read Postamble t IS t IH MEMDATA WD1 WD2 WD3 WD4 CL=2.5 DQS DQS Read Preamble DQS Read Postamble MEMDATA WD1 WD2 WD3 WD4 30

32 A couple of items to keep in mind on the DQS module: Designing with DDR SDRAM Route all byte lane signals together. The DQS module only delays the DQS incoming strobe, so keeping all 8 data lines matched in length, helps guarantee that the data valid window will be the same for the whole byte lane. In general I always route the 8xDQ lines, the matching DQS, and DQM to the same tolerances. Matching the four byte lanes is important, but its more of a general guideline. The DQS block can easily tolerate 1-2 inches of trace difference across all data lines. Typically on FR4 systems I use 180ps per inch when estimating trace delay. So a 1-2 inch skew across the bus only equates to about 360ps of mismatch. 31

33 Designing with DDR SDRAM DDR(I) systems typically use a 2.5V SSTL I/O instead of a LVCMOS or LVTTL style I/O. SSTL I/Os provide a differential receiver and typically are used with series and parallel termination. When designing DDR buses, please encourage your customers to use IBIS models to simulate their layout constraints. Placement of logic analyzer connectors should be carefully analyzed, because capacitive loading can affect overall signal quality. Mictor connectors are not recommended for DDR. 32

34 Designing with DDR SDRAM Here are some examples of some DDR terminations Volts The first diagram is a typical series-parallel termination scheme. Rs T-line: 50 ohm VREF = 1.25V Rp SSTL Input Buffer The second diagram shows a series parallel termination. But this one is specific to DDR DIMMs and how the DIMM manufacturers actually use a single resistor between the two clock phases. Differential Output Buffers. Memory Clock Outputs Rs Rs T-line: 50 ohm T-line: 50 ohm Rp SSTL Input Buffer 33

35 Designing with DDR SDRAM Sample layout information The MCU is located in the top left side of the picture. Series terminators (RPacks) are located close to the package. Then LA connectors (Tektronix compression style). Then DIMM through hole connector Then parallel terminators. Make sure to route a metal plane from your VTT regulator to all the parallel terminators. 34

36 Designing for FlexBus FlexBus is a new enhanced/modified version of the old ColdFire external bus module. FlexBus gets its name from being flexible and offering customers a muxed and/or non-muxed bus with a minimal amount of pins. Same general concerns: Make sure to use pull-up resistors on active low control signals. Need to use an address latch when in 32-bit muxed mode. 35

37 Designing for PCI The PCI bus is standalone and not muxed with the FlexBus or DDR bus and careful board design decisions should be made. Typically, a customer can get up to two external devices to work at 66Mhz. Typically, a customer can get up to four external devices to work at 33Mhz. PCI is inherently a noisy bus, because the number of parallel stubs and the size of the typical PCI output buffer. The 547x and 548x PCI buffers are capable of driving large capacitive loads and still meet timing. The result is fast edge rates that can cause signal integrity problems. Make sure to use a PTP (point-to-point) clocking system. Pick a clock source Mhz Using a zero-delay buffer, route a PTP clock line to each PCI device and to the MCF547x or 8x. 36

38 Designing for USB The MCF547x and MCF548x have a USB 2.0 HS capable PHY that is built into the part. Route the DP and DM signals as 90-ohm differential pair. I typically suggest routing these on the top or bottom layer with no vias if possible. The PHY has series termination built into the PHY. 37

39 68K/ColdFire: Web Resources 68K/ColdFire Home Page Latest documentation Application notes Reference Designs Evaluation board schematics Links of interest Sample code 68K/ColdFire Discussion Groups Expert advice from the developer community moderated by Freescale 68K/ColdFire application engineers Historical 68K/ColdFire discussion group not affiliated with Freescale 38

40 Freescale Support World-Class Application Engineering Support Comprehensive world-wide applications team. Support in Europe, Asia, and the Americas. Submit technical questions: Web: 39

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