5. ARM 기반모니터프로그램사용. Embedded Processors. DE1-SoC 보드 (IntelFPGA) Application Processors. Development of the ARM Architecture.

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1 Embedded Processors 5. ARM 기반모니터프로그램사용 DE1-SoC 보드 (IntelFPGA) 2 Application Processors Development of the ARM Architecture v4 v5 v6 v7 Halfword and signed halfword / byte support System mode Thumb instruction set (v4t) Improved interworking CLZ Saturated arithmetic DSP MAC instructions Extensions: Jazelle (5TEJ) SIMD Instructions Multi-processing v6 Memory architecture Unaligned data support Extensions: Thumb-2 (6T2) TrustZone (6Z) Multicore (6K) Thumb only (6-M) Thumb-2 Architecture Profiles 7-A - Applications 7-R - Real-time 7-M - Microcontroller Note that implementations of the same architecture can be different Cortex-A8 - architecture v7-a, with a 13-stage pipeline Cortex-A9 - architecture v7-a, with an 8-stage pipeline 3 4

2 ARM Cortex-A9 ARM Cortex-A9 MPCore Application-level processor included in Cyclone V SoC-FPGA 1-2 Cores Features: 800 MHz 32-bit processor 32 KB instruction and data L1 caches Snoop control unit (SCU) Accelerator Coherency Port (ACP) Unified 512KB L2 Cache ARM NEON single instruction, multiple data (SIMD) coprocessor Floating point unit CPU 0 ARM Cortex-A9 SIMD and FPU MMU I-Cache D-Cache Private Timers CPU 1 ARM Cortex-A9 SIMD and FPU MMU I-Cache D-Cache Private Timers Generic Interrupt Controller Accelerator Coherency Port and Snoop Controller 5 6 DE1-SoC Cyclone V SoC FPGA Cyclone V SoC FPGA Dual-core ARM Cortex-A9 1GB DDR 3 SDRAM, MicroSD USB, Triple-speed Ethernet ADC, Accelerometer LED, Pushbutton FPGA 85K Programmable Logic Elements 64 MB SDRAM DVD-quality audio in/out, Video in/vga out PS/2, IrDA 4 debounced pushbuttons, 10 slider switches, 10 red LEDs, six 7-segment displays Expansion headers Built-in USB Blaster for FPGA programming HPS 7 8

3 Assembler Directives Altera (IntelFPGA) Monitor Program Directives provide information required by the assembler GNU Assembler directives.text Identifies code section.global symbol Makes symbol visible outside the assembled object file.word expressions.end Comma separated expression are assembled into 32-bit numbers Marks the end of the source file DE1-SoC 의 ARM Cortex-A9 프로세서용프로그램을컴파일, 어셈블, 다운로드및디버그하는데사용되는프로그램 호스트 PC 에서수행되며 DE1-SoC 의 ARM 기반시스템과통신수행 9 10 Exercise 1 Conditional Execution Create a software project targeting the ARM Cortex-A9 Compile the application Download the compiled software to the DE1-SoC Run and debug the application Most ARM instructions are executed conditionally. ADD R2, R3, R4 (always execute) ADDAL R2, R3, R4 ADDNE R2, R3, R4 (execute only if the Z flag is clear) Example: c = (a > b)? (a b) : (b a); START: CMP R0, R1 START: CMP R0, R1 BLT LESS SUBGT R2, R0, R1 SUB R2, R0, R1 SUBLE R2, R1, R0 B END LESS: SUB R2, R1, R0 END: 11 12

4 Exercise 1: Greatest Common Divisor (GCD) int a = 54, b = 24; do { if ( a > b) a = a b; else b = b a; } while (a!= b); Exercise 1: Greatest Common Divisor (GCD) int a = 54, b = 24; do { if ( a > b) a = a b; else b = b a; } while (a!= b);.text.global _start _start: MOV R0, #54 /* Register R0 is the first number. */ MOV R1, #24 /* Register R1 is the second number. */ GCD: CMP R0, R1 /* Set the condition codes. */ SUBGT R0, R0, R1 /* If (R0 > R1) then R0 = R0 R1. */ SUBLT R1, R1, R0 /* If (R0 < R1) then R1 = R1 R0. */ BNE GCD /* If (R0!= R1) then loop again. */ STOP: B STOP /* If (R0 == R1) then stop. */.end Step 1: Start Altera Monitor Program Step 2: Create a New Project Sets up the Altera Monitor Program Select files to work with Specify target system 15 16

5 Step 2.1: Specify name, directory and architecture Step 2.2: Select the ARM Cortex-A9 System Step 2.3: Select Program Type Step 2.4: Add Source File 19 20

6 Step 2.5: Set Board Connection, Select Processor Step 2.6: Leave Default Memory Settings Step 3: Compile and Load Compile your assembly language program Load the compiled code into the memory on the DE1-SoC board 23 24

7 Disassembly Registers Info & Error Msgs Terminal 27 28

8 29 30 Step 5: Single Step your Program Step 5: Single Step your Program 31 32

9 Step 6: Change Register View Step 7: Single Step your Program Again Step 8: Set a Breakpoint Step 9: Run to the Breakpoint 35 36

10 Step 9: Run to the Breakpoint Step 10: Change Register View Step 11: Look at CPSR Step 11: Look at CPSR 31 N 30 Z 29 C 28 V 7 I 6 F 5 T N 30 Z 29 C 28 V 7 I 6 F 5 T Condition code flags Interrupt disable bits Processor mode ARM or Thumb operation CPSR = 0x200001D3 What should have happened in our code? GCD: CMP R0, R1 SUBGT R0, R0, R1 SUBLT R1, R1, R0 BNE GCD Note GT is Z clear and N equals V LT is N is not equal to V NE is Z clear 39 40

11 Step 12: Set a Breakpoint at the End and Run Step 13: Restart the Program Step 14: Single Step Step 15: Modify R

12 Step 16: Run to Breakpoint Step 17: Disconnect from the DE1-SoC Board 45 46