Introduction to the Tegra SoC Family and the ARM Architecture. Kristoffer Robin Stokke, PhD FLIR UAS

Transcription

1 Introduction to the Tegra SoC Family and the ARM Architecture Kristoffer Robin Stokke, PhD FLIR UAS

2 Goals of Lecture To give you something concrete to start on Simple introduction to ARMv8 NEON programming environment Register environment, instruction syntax «Families» of instructions Important for debugging, writing code and general understanding Programming examples Intrinsics Inline assembly Performance analysis using gprof Introduction to GDB debugging

3 Keep This Under Your Pillow GNU compiler intrinsics list: o ARM Infocenter o infocenter.arm.com -> developer guides (..) -> software development -> Cortex A series Programmer s Guide for arm8 This may also be useful Last but not least GDB You will need it

4 5 Tegra Family of SoCs Tegra family of mobile Systems-on-Chip (SoC) Family of mobile SoCs Quite sophisticated Many knobs for tuning, experimentation and research! Wide operational range: runs at 2 W -> 20 W Frequency (clock) scaling Heterogeneous processors ( CPU / GPU ) CPU Tegra K1 Tegra X1 Tegra X2 Tegra Xavier High Performance 4 x ARM Cortex-A15 4 x ARM Cortex-A57 Dual-core Denver 8 core Carmel CPU Low Power 1 x ARM Cortex-A15 4 x ARM Cortex-A53 4 x ARM Cortex-A57 GPU 192-Core Kepler 256-Core Maxwell 256-Core Pascal 512-Core Volta Memory 2 GB (Jetson-TK1) 4 GB (Jetson-TX1) 8 GB LPDDR4? GB LPDDR4 9/10/2018 armv8

5 Tegra-Powered Servers System-on-Module (SoMs) mounted in a 1U server. Very dynamic power usage depending on load: Jetson TX2 / TX1 blade server with 24 SoMs. Based on my own guess.. I would say anything between 80 W to 500 W, depending on demand for processing power

6 Frequency Scaling Moden chips can changing clock frequency Power <-> Performance Tradeoff Processor / memroy utilisation typically varies throughout time Power and powerformance over processor and memory frequencies. The ondemand governor [1] Idea is to reduce CPU frequency while idle or under busy I/O computation Other governors exist for RAM, GPU, buses etc CPU utilisation over time for the Sort application. [2] [1] Pallipadi, Venkatesh, and Alexey Starikovskiy. "The ondemand governor." Proceedings of the Linux Symposium. Vol. 2. No sn, [2] Ibrahim, Shadi, et al. "Governing energy consumption in Hadoop through CPU frequency scaling: An analysis." Future Generation Computer Systems 54 (2016):

7 CPU interrupt controller Coresight (debug hardware support) IRAM and separate ARM7TDMI core Global interrupt control, Clock controllers, timers etc CPU Complex Bus / Interconnect Mainly AXI (highperformance bus), bridges 256-bit CPU interface to RAM I2C / SPI I/O Hardware filters VIC Post-process video Rotation, scaling, comp. VI (Video Input) Raw (YUV, BAYER) processing 2x ISPs (hidden) NVENC/NVDEC Video encode Video decode NVJPG RAM Tegra X1 Block Diagram SATA, USB, MIPI, HDMI etc. I/O

8 Tegra X1 CPU and Memory Hierarchy Each core with various compute capability Integer, floating point NEON (SIMD) Four Cortex-A57 cores, each.. 48 kb instruction L1 cache 32 kb data L1 cache One shared, 2 MB L2 cache Instruction + data Least-Recently Used (LRU) eviction policy 64 byte cache lines 32-bit interface to RAM.. Tegra K1 CPU and memory overview, which is similar to that of the TX

9 Cache Hierarchies and Performance Let s do an experiment! Reading or writing 800 MB Vary the size to read back-to-back E.g. read 24 kb repeatedly from same buffer, until 800 MB have been read CPU Core 33k 24 kb L1 Cache 32 kb Read 800 MB Buffer size detemines location of data Below 32 kb, all reads are cached in L1 Below 2 MB, all reads are cached in L2 For 10 MB... Nothing gets cached 12k 64 kb L2 Cache 2 MB 1k 800 MB RAM 4 GB

10 Time [ms] Code Example and Profiling Compile with pg Run application:./main Run gprof./main gmon.out NB: Prefetch op Prfm <type><target><policy> reg label Type pld (for load) pst (for store) pli (for instruction) Target L1 or L2 (or L3) Policy keep (normal) stream (use once) prfm pldl1keep [x0] (address in x0)

11 ARMv8 Registers 31 x 64-bit general purpose registers X0 X8 x16 x24 32 x 128-bit vector registers V0 V8 V16 V24 SP WSP Stack pointer WZR XZR Zero registers PC

12 The Vector Registers V0-V31: Packing Data in V0-V31 are packed, and you control how they are packed Example: 16 bytes or 8 bytes Example: 8 half-words or 4 half-words Lanes

13 Example: Vector Packing

14 Instruction Syntax

15 Programming With Intrinsics More in a bit!

16 Programming Example: Intrinsics

17 Inline Assembly Mostly harder than using intrinsics However, gives more control (and better performance?) Not always straightforward to figure out what mnemonics to use Tips: disassemble intrinsics and look with objdump or gdb Operand constraints > «m» : memory address > «r» : general purpose register > «f» : floating point register > «i» : immediate ++ more Specify dirty registers and more

18 Programming Example: Inline Assembly

19 Table Lookup Not straightforward to use for any purpose Vector table lookup: vtbl v0, {v1, v2,..., vn}, vm V0: destination vector {v1, v2,..., vn}: source data vm: data selector v v1 v vm

20 Matrix Transpose tbl v0.4s, {v1.4s}, v2.4s a b a c a c b d v0.4s c d b d v2.4s stride Think like this: For each output row, select increasing column a stride b c d v1.4s

21 Code Profiling Compile with pg Run application:./main Run gprof./main gmon.out Time to Finish 100M computations for Matrix Multiply (MM) and Transpose Operations? Transpose, lazy Transpose, NEON assembly MM, NEON intrinsics Series 1 Column1 Column2 MM, NEONassembly

22 GDB Example

23 Tips Build functions to print out macroblocks from vector registers and memory Start small test out independent parts of the code that are easy to verify When in trouble, step through the code, display the relevant registers, verify with output you know is working Many things to investigate Single versus double precision? Different, possibly more ways to implement e.g. transpose? Re-using vector registers across different functional blocks?..but stick to what the assignment says

24 Good Luck! You re going to need it

25 ARMv7 vs. ARMv8 Armv8 uses the same mnemonics as for general purpose registers E.g., in ARMv7, «mul, r0, r0, r1» (normal) and «vmul d0, d0, d1» (SIMD) In ARMv8: «mul x0, x0, x1» (normal) and «mul v0, v0, v1» (SIMD) Simplifies life, but take care to use correct operands ARMv8 has twice as many 128-bit registers bit registers, vs bit registers for ARMv7 Different instruction syntax

26 27 Tegra K1: a Mobile Heterogeneous Multicore SoC Quad-core highperformance CPU ARM Cortex A15 Frequency scaling Dedicated lowpower core ARM Cortex A15 Frequency scaling 192-core, Keplerbased GPU CUDA programmable Frequency scaling SIMD (NEON) multimedia instructions 2 GB DDR3 RAM CPU-GPU shared Frequency scaling