DynamIQ Processor Solutions (Using Cortex- A75 & Cortex-A55) for 5G Networks & Mobile

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1 DynamIQ Processor Solutions (Using Cortex- A75 & Cortex-A55) for 5G Networks & Mobile Satoshi Nakajima FAE manager Arm Norio Kisumi Sr Manager, Operator Relations Arm 2017 Arm Limited Arm Tech Symposia 2017

2 5G Networks 2017 Arm Limited

3 5G Technical Requirement (3GPP Release-15 and beyond) 5G Target Enhancement from 4G embb (enhanced Mobile BroadBand) Throughput >10Gbps Mobility 500km/h 100x 1.5x URLLC (Ultra-Reliable and Low Latency Communications) Latency <1mS Reliability % 30 50x 10x mmtc (massive Machine Type Communications) Density 1M-device/km 2 Battery Life >10years x 100x energy efficiency Arm Limited

4 5G Dynamics Across the Network: Edge to Cloud Compute IoT, Automotive, Industrial, Medical S A C S C A C C S A S C C A Storage Storage Storage ion ion Acceleration Packet Flows Packet Flows Packet Flows Devices New Radio Technology Heterogeneous Network Network Virtualization Network Slicing Mobile Edge Computing Arm Limited Access/Edge Edge Compute require computing platform to be more Core / DC Flexible Scalable Diverse Performance Energy efficient

5 4G logical RAN architecture RU RU Remote Unit (RU) enodeb Distributed Unit () Management and control enb RU RU RU RU Radio Radio Radio Radio CPRI L1 / Phy MAC RLC PDCP EPC enb S6a S11 HSS MME SGW S5 Evolved Packet Core (EPC) Gx PCRF PGW RU : Radio Unit : Distributed Unit EPC : Evolved Packet Core enb RU RU RU RU enb RU RU Arm Limited Source : Ericsson review, 3GPP TR

Next gen logical RAN architecture RU RU RU RU EPC/NGC CU RU RU gnb RU : Radio Unit : Distributed Unit EPC : Evolved Packet Core CU: Central Unit NGC : Next Generation

6 Next gen logical RAN architecture RU RU RU RU EPC/NGC CU RU RU gnb RU : Radio Unit : Distributed Unit EPC : Evolved Packet Core CU: Central Unit NGC : Next Generation Core Central Unit (CU) Management Switch PDCP RU RU Distributed Unit () RU RU RU RU L1 / Phy Management MAC RLC Arm Limited Source : Ericsson review, 3GPP TR

7 Network/Wireless Infrastructure: Three Distinct Segments Two Distinct Approaches Typically standardized platform designs 5G Antenna MEC Core Network/Data Centre CPU Server Server Air Interface Processing Base Station Network And RAN Offload Network Offload Typically customized platform designs Arm Limited

8 Network/Wireless Infrastructure: Edge Access Packet processing / front end / edge design. Arm: Meet diverse needs with heterogeneous platforms Mix of latency, throughput and power Supplement sub-systems approach with accelerator offload. Sub-system/packet processing platform ASIC based designs and dedicated platforms Merchant Silicon from multiple suppliers CCIX and connection to FPGA technology Arm Limited 5G Antenna CPU Air Interface Processing Edge Network Architecture 5G Air Interface Management Antenna, RRH, DFE, Distributed Base Band, Multi-Access Compute Acceleration. IoT Gateway and End applications. Optimized power, performance, latency Hardware acceleration for advanced signal processing and terabit throughput. Base Station Customized platform designs

9 Network/Wireless Infrastructure: Core Network Leverage energy efficient Arm servers with specifics for network infrastructure Linaro Server group activity, VNF porting activity, OPNFV actions, AIDC, OSEC Server-like Architecture more efficient on Arm Core Network/Data Centre Standardized general purpose compute platforms on Arm Performance/Density/Scalability Support dedicated offload through silicon/software. DPDK/ODP support 5G Network Hierarchy Design Multi-Access Edge Compute, Distributed Evolved Packet Core, Distributed Applications Processing, Distributed Content Delivery Application of virtualized/containerized workloads Control plane functions, content and applications delivery can use general purpose virtualized cloud computing. Server Network Offload Arm Limited

10 Network/Wireless Infrastructure: Mobile Edge Compute Workload optimized general purpose compute and accelerators for user plane processing. MEC Edge Compute Architecture MEC will be critical in meeting 5G goals Low latency, low power required E2E Automotive assisted driving, IoT and industrial use cases 5G network Slicing dependent Designs range from chassis, multi chip to SOC designs Server Network And RAN Offload Unique designs tailored to MEC form factor will prevail. Mix of: Core network needs (software driven, compute performance) Edge Network needs (Latency, throughput, power optimized) 5G network slicing power and latency Arm Limited

11 Wireless Infrastructure Market Influence & Timescales 5G Phase Pre-5G Phase Broad-band Mesh 5G Specifications Early 5G deployments LTE-Advanced Pro WRC-15 Frequencies (sub 6GHz) WRC-19 Frequencies (5G cm & mm up to 100GHz) Common 3G/4G Edge and Core Network Broadband Mesh & Metro WiFi (WiGIG) 5G vol. ramp Technology Preparation 5G NG Cellular drivers: 5G/LTE-Pro as wireline replacement for last mile. Speed over features LTE-Pro as a testing ground for new antenna algorithms. Beam forming and MIMO Re-Farmed spectrum and channel aggregation allows 4G to stretch to high throughput needs MEC driven by new uses and traffic type NFV Early Deployment/Core Enhanced Security Requirements Distributed L1/L2) processing 5G Mesh antenna Massive MIMO, Beamforming Edge Cloud/MEC Early Deployments OPNFV Deployments/Core Arm Limited

12 DynamIQ Processor Solutions 2017 Arm Limited

13 Networking requires diverse platforms Storage GPP Acceleration Networking vcpe GPP Accel Mem GPP GPP Accel PLD NPU Acceleration Storage Edge content caching Networking & optimization GPP Wireless-access-point / vcpe GPP GPP NPU Switch / router blade GPP GPP GPP GPP GPP GPP GPP GPP Acceleration Storage Networking GPP NFV appliance DSP DSP GPP DSP NPU PLD GPP GPP GPP GPP GPP GPP GPP GPP Base station / modem Scale out / server Arm Limited

14 New DynamIQ-based CPUs for new possibilities Arm Cortex-A75 Arm Cortex-A x x x x x x Baseline to Cortex-A72 Baseline to Cortex-A53 All comparisons at ISO process and frequency All comparisons at ISO process and frequency Arm Limited

Cache stashing and atomic operations improves multicore networking performance and improves latency.

15 Next-generation features Dot product and half-precision float for AI/ML processing. Virtualized Host Extensions (VHE) offering Type-2 hypervisor (KVM) performance improvements. Cache stashing and atomic operations improves multicore networking performance and improves latency. Cache clean to persistence to support storage class memory. Infrastructure class RAS enhancement including data poisoning and improved error management Arm Limited

16 DynamIQ Shared Unit (DSU) Support for multiple performance domains Core 0 DynamIQ cluster 0-7 Cores Core 7 Latency and bandwidth optimizations DynamIQ Shared Unit (DSU) Streamlines traffic across bridges Snoop filter L3 Cache Asynchronous bridges Bus I/F ACP and peripheral port I/F Power Management Advanced power management features Supports large amounts of local memory Scalable interfaces for edge to cloud applications Low latency interfaces for closely coupled accelerators Arm Limited

17 Increasing performance through cache stashing Enables reads/writes into the shared L3 cache or per-core L2 cache. Allows closely coupled accelerators and I/O agents to gain access to core memory. AMBA 5 CHI and Accelerator Coherency Port (ACP) can be used for cache stashing. More throughput with Peripheral Port (PP) for acceleration, network, storage usecases. Core0 L1 cache L2 cache Snoop filter Accelerator or I/O Stash critical data to any cache level DynamIQ cluster 0 7 Cores DynamIQ Shared Unit (DSU) L3 Cache Asynchronous bridges Cortex-A CPU CPU CPU L2 L2 Cache L2 L2 Cache Cache L3 Cache Bus I/F Agile System Cache ACP and peripheral port I/F CoreLink CMN-600 Core7 L1 cache L2 cache Power Mngmt Cortex-A CPU CPU CPU L2 L2 Cache L2 L2 Cache Cache L3 Cache Agile System Cache DMC-620 DMC Arm Limited DDR4 DDR4

18 Networking: Compute and packet-processing solution Build the right mix of compute High-performance Cortex-A75 High-efficiency throughput Cortex-A55 DSP, accelerators Data plane processing Throughput compute Optional local accelerators Control plane processing Performance compute Timing critical processing Scale CoreLink CMN-600 for application Cortex-A55 Level-3 Cache Local Accelerator Cortex-A75 Level-3 Cache DSP Access points: 2~5W Macro BTS: 20~30W Agile System Cache CoreLink CMN-600 Agile System Cache IO IO Ethernet Telecom server: 60~100W DMC-620 DMC-620 Accelerator Scalable coherent SoC memory system Arm Limited

19 DMC-600 DDR PCIe PCIe CML CML DMC-600 DDR Data center server blade: Maximize compute density Cortex-A75 can deliver 1.4x to 2.9x higher performance. DDR DMC-600 PCIe 100GbE DDR DMC-600 >1.4x performance with 32 core Cortex-A75 + CMN-600 vs. 32 core Cortex-A72 + CCN-512 DDR DMC-600 Cache Cache Cache Cache 2.9x performance with 64 core Cortex-A75 +CMN-600 Higher rate performance than competitive architectures per socket Cache Cache Cache Cache 1-1.5W/core enables sustained operation at maximum performance Power: 60W compute. DDR DMC-600 Cache Cache Cache Cache Cache Cache Cache Cache DMC-600 DMC-600 DDR DDR Arm Limited

20 まとめ 5G でモバイルネットワークは大きな変換期を迎えます多様なユースケースに対応する仮想化やネットワークスライス技術モバイルエッジコンピューティング (MEC) に要求される相反する機能の両立サーバ的な要求 ( ソフトウェアベース高いコンピューティング性能汎用性 ) とエッジネットワークの要求 ( 低遅延高スループット電力効率 ) RAN~Edge~Core~Data Center プラットホームの互換性柔軟性およびスケーラビリティアームでは DynamIQ は高いコンピューティング性能と消費電力の最適化を両立させかつ優れた拡張性を提供することで真のスケーラブルな SoC 開発を可能にします Arm とエコシステムパートナーより提供されるソフトウェアによって 5G ネットワーク開発を支援します Arm Limited

21 Thank You! Danke! Merci! 谢谢! ありがとう! Gracias! Kiitos! Arm Limited

22 The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners Arm Limited

DynamIQ Processor Designs Using Cortex-A75 & Cortex- A55 for 5G Networks

DynamIQ Processor Designs Using Cortex-A75 & Cortex- A55 for 5G Networks 2017 Arm Limited David Koenen Sr. Product Manager, Arm Arm Tech Symposia 2017, Taipei Agenda 5G networks Ecosystem software to support