Evolving IP configurability and the need for intelligent IP configuration

Transcription

1 Evolving IP configurability and the need for intelligent IP configuration Mayank Sharma Product Manager ARM Tech Symposia India December 7 th 2016

2 Increasing IP integration costs per node $140 $120 $M $133 $100 $80 $60 $40 $20 $0 $91 $61 $41 $23 350nm 250nm 180nm 130nm 90nm 65nm 40nm 28nm 20nm 14nm 10nm 7nm Semico Research and Consulting Group IP integration is becoming a major design effort 2

3 IP configurability and integration is evolving IP configurability is evolving because Highly complex subsystems Increasing IP reuse Competitive IP market IP configuration challenges Configurability is becoming IP-specific Detailed documentation is required to describe the IP configurability Today s methodologies for managing IP configurability is making efficient and reusable IP integration more difficult 3

4 Complexity IP configurability complexities Configurable µarchitecture Configurable interfaces RTL parameterization Static IP 4

5 Complexity IP configurability solutions Native RTL support Scripted string manipulation High-level modeling µarchitecture creation Logic/interface conditionality Port-width parameterization Static RTL 5

6 IP configurability IP configurability complexity CL-3 CL-2 Power/clock/reset infrastructure Complex interconnects Ad-hoc subsystems Debug & trace CL-0 : No configurability CL-1 CL-0 Interrupt infrastructure CPUs GPUs Memory management infrastructure Mini-systems Build complexity Constrained subsystems CL-1 : Low complexity (10s of parameters) CL-2 : Medium Complexity (100s of parameters) CL-3 : High complexity (1000s of parameters) 6

7 Managing IP configurability and complexity 7

8 IP configurability Managing IP configurability and complexity CL-3 CL-2 CL-1 CL-0 Interrupt infrastructure CPUs IP builders GPUs Power/clock/reset infrastructure Memory management infrastructure Mini-systems Complex interconnect s Build complexity Ad-hoc subsystems Debug & trace IP creators Constrained subsystems IP builders employ RTL rendering flows to configure & build IP IP creators configure, create and integrate IP based on system-level configurations and dependencies 8

9 CL-1 configurability example requiring an IP builder The number of processors (1-4) L2 cache size L2 Tag and Data RAM register slices L2 arbitration logic register slice L1 ECC/Parity support L2 ECC support Number of L2 FEQ entries ACE or CHI Cryptography engine included GIC CPU interface is included ACP is included 9

10 IP builder flow Parse IP configuration specification containing a list of all parameters Check parameters for the correct values and any interdependencies Build design including Verilog, testbench and RTL implementation setup (e.g. SDC, UPF, LEC) 10

11 DMC-620 DMC-620 CL-3 configurability example requiring an IP creator Scalable, heterogeneous compute from edge to cloud Scales from 1 to 256 cores Simplify software & deployment with common architecture Integrated, agile system cache Cache size from 0MB to 128MB Shared cache for CPU & IO Integrated Snoop Filter Lowest Latency with DMC to 8 DDR controllers End-to-end QoS & RAS Coherent Mesh Network CMN-600 DMC-620 PCIe 100GbE DMC-620 CPU CPU CPU CPU CPU CPU CPU CPU CoreLink CMN-600 CPU CPU CPU CPU CPU CPU CPU CPU DMC-620 DMC-620 DMC-620 DMC

12 IP creator flow Harvest system meta-data to populate IP specification Complete the IP specification with advanced specifications Create µarchitecture automatically Generate RTL, testbench, SDC and UPF deliverables 12

13 An IP tooling driven solution for intelligent IP configuration and integration 13

14 IP tooling that simplifies ARM-based system design CoreSight Creator CoreLink Interconnect CoreSight Debug & Trace Subsystem Tool that makes configuration of CoreSight IP simple and automatically creates your CoreSight system that is right first time. CoreLink Creator Tool that makes configuration of CoreLink IP simple and automatically creates your CoreLink interconnect system that is right first time. SoC Socrates DE Tool that enables intelligent configuration and integration of ARM IP to quickly and easily build ARM-based systems 14

15 Configure CL-1 and CL-2 IP with an IP builder IP configuration Define parameters Validate configuration Create configured IP with underlying IP builder 15

16 Define SoC Bill of Materials (BOM) System BOM Instantiate configured IP Instantiate system IP Validate BOM 16

17 Intelligently configure CL-3 IP with an IP creator Harvest System data Identify debug & trace interfaces Identify interconnect interfaces Automatically create system specification 17

18 Automatically create system IP µarchitecture µarchitecture Design algorithms configure and infer ARM system IP Automatically created Refinement Flow DRCs 18

19 Faster and easier system assembly System assembly Automated AMBA connectivity Meta-data driven IP integration Correct-by-construction 19

20 Automatic RTL generation Generated deliverables RTL design C models Testbench & test cases Constraints Design spec & reports 20

21 Summary Intelligent IP configuration Automated IP integration enabled by intelligently configured IP and system context Future innovation to encompass constraints, software & security Intelligently configure IP and reduce the time to assemble systems to days, not months 21

22 The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright 2016 ARM Limited