PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL UPDATE

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1 nc. PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL UPDATE DTACK GENERATOR DATE : 2 NOV 98 The DTACK Generator is a state machine. It delays the memory or I/O access cycle of the PC Card when the card asserts the signal. The state diagram is shown in Figure 0-1 *CSD3=0 S3 10 *CSD3=1 *CSD3=1 S0 00 S2 11 *CSD3=0 S1 01 =0 Figure 0-1. DTACK Generator State Diagram All the state transitions take place at rising edge of the system clock. The state machine can be implemented by following circuit. MOTOROLA PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL 1

2 nc. A B C D E CLK VCC U1B U3A 5 6 D0 2 D Q 5 3 U1A 7LS00 CLK *Q1 1 *Q0 Q HC7 U2A 7LS00 *CSD3 1 2 *CSD3 7HC0 12 Q113 U1D 11 7LS00 U1C U3B D1 12 Q1 D Q 9 *Q0 9 7LS00 11 CLK Q 8 *Q1 2 2 UA 2 18 A1 Y1 16 A2 Y2 6 1 A3 Y3 U2B 8 12 A Y D1 7HC0 VCC 13 CL PR 10 1 CL PR 3 7HC7 1 G 7HC20 MOTOROLA HIGH PERFORMANCE EMBEDDED SYSTEMS 2 DAI KING ST, TAIPO IND EST 1 TAIPO NT HK 1 Title DTACK GENERATOR Size Document Number Rev CustomHE A B C Date: Tuesday, November 2, 1998 Sheet 2 of D E

3 Design Document nc. State S0 stands for the time when both *CSD3 is negated. There is no card access activities. When *CSD3 is asserted, the state machine transits to state S1. Then after a clock, it transits to state S2. After the PC Card has asserted the signal, the state machine holds in state S2. Beginning from S2, is generated from inverted signal which is implemented as follows. D1 When state machine is in S2 or S3, D1 asserts and enables the inverter. Therefore when asserts, is negated and when negates, is asserted. *CSD3 When there is no asserting in the cycle, will assert after S2 until S0. *CSD3 S2 After signal is negated, the state machine transits to S3. When the *CSD3 negates, it returns to S0 and D1 negates and disables the invertor so that returns to high impedance state. 2 PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL MOTOROLA

4 DECODER nc. Design Document It is implemented by a PAL22V10. It decodes the DragonBall control signals and generates the PCMCIA control signals. In this application, all the I/O space and memory space inclucding attribute memory and common memory in the PC card are selected by *CSD3. The DragonBall has to assert *REG(PM2 = 0), while accessing the attribute memory space. To access common memory, DragonBall has to negate *REG(PM2=1). To access I/O, DragonBall has to assert IOEN (PJ) and *REG. The following is the updated PAL equation with only one chip select used. TITLE PCMCIA VER 2.01 DECODER AUTHOR JACKY LI COMPANY MOTOROLA INC. DATE 23/11/98 REVISION PATTERN CHIP U1 PAL22V10 ;PIN CLK IOEN /CSD3 /UDS /LDS /LWE NC /OE /WE /UWE /BUFF GND ;PIN NC Q DIR /G /BOE /BWE /IOW /IOR NC /CE2 /CE1 VCC GLOBAL EQUATIONS CE1 = UDS * CSD3 + LDS * CSD3 CE1.TRST = BUFF CE2 = UDS * LDS * CSD3 CE2.TRST = BUFF IOR = CSD3 * IOEN * OE IOR.TRST = BUFF IOW = CSD3 * IOEN * LWE + CSD3 * IOEN * UWE IOW.TRST = BUFF BWE = /IOEN * WE * CSD3 BWE.TRST = BUFF G = CSD3 * BUFF DIR = /OE + WE BOE = /IOEN * OE * CSD3 BOE.TRST = BUFF MOTOROLA PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL 3

5 Design Document nc. As you can see from the PAL equation, the signals are generated by simple logic, therefore logic gates can be used instead of PAL to implement this decoder. 0.1 MEMORY MAP The PCMCIA interface memory map is shown in Fig x Common Memory *REG = 1 0XBFFFFF 0.2 INITIALIZATION CODE Attribute Memory (IOEN=0) or I/O Space (IOEN=1) *REG = 0 Figure 0-2. PCMCIA Interface Memory Map In Init_CS, PJ is set as I/O port. (write 0xfff3b=0x1F) CSD3 selects address range 0x to 0xBFFFFF and external DTACK is used. nop *************BEFORE INSERTING CARD ************ nop Init_CS write 0xfff3b -b = 0x1F write 0xfff1c -l = 0x80013ff7 nop Buffer_Off write 0xfff1 -b = 0xFE nop AttrMem_Off write 0xfffb -b = 0x06 write 0xfff9 -b = 0xff write 0xfff8 -b = 0x00 nop *************AFTER INSERTING CARD ************ PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL MOTOROLA

6 Design Document nc. nop Vcc_On write 0xfffb -b = 0x1E write 0xfff9 -b = 0xE7 write 0xfff8 -b = 0x1C nop Buffer_On write 0xfff3 -b = 0x3C write 0xfff1 -b = 0xEE write 0xfff0 -b = 0x10 nop C_Reset write 0xfffb -b = 0x1E write 0xfff8 -b = 0x1C write 0xfff9 -b = 0xE7 nop AttrMem_On write 0xfffb -b = 0x1E write 0xfff9 -b = 0xE3 write 0xfff8 -b = 0x1C ************************************ To read attribute memory, type read 0x To read I/O space, type write 0x b = 0x1 write 0xfff38 -w = 0x10f5 Note: Port PJ is set to output port and to assert IOEN. 5 PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL MOTOROLA