ECE 270 Learning Outcome Practice Exam B. OUTCOME #2: an ability to analyze and design combinational logic circuits.

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1 ECE 70 Learning Outcome - - Practice Exam B OUTCOME #: an ability to analyze and design combinational logic circuits. Multiple Choice select the single most appropriate response for each question. Note that none of the above M be a VLID NSWER. Place answers on the supplied BUBBLE SHEET only nothing written here will be graded.. Most logic minimization methods are based on a generalization of: () the covering theorem (B) the combining theorem (C) the consensus theorem (D) DeMorgan s Law. If the function (,,Z) is represented by the ON set,,z(0,,4,7), then the dual of this function D (,,Z) is represented by the ON set: (),,Z(0,,4,7) (B),,Z(,,4,6) (C),,Z(,,5,6) (D),,Z(,,4,7). The property listed below that is NOT true for OR gates is: () ssociativity (B) commutivity (C) distributivity (D) idempotency 4. The circuit shown below exhibits the following type of hazard when its input,, transitions from high-to-low: () a static-0 hazard (B) a static- hazard (C) a dynamic low-to-high hazard (D) a dynamic high-to-low hazard 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

2 ECE 70 Learning Outcome - - Practice Exam B The following K-map applies to questions 5 through 8: W W d 0 Z 0 0 Z 0 d 0 d 0 Z 5. ssuming the availability of only true input variables, the fewest number of -input NND gates that are needed to realize this function is: () 6 (B) 7 (C) 8 (D) 9 6. ssuming the availability of only true input variables, the fewest number of -input NOR gates that are needed to realize this function is: () 6 (B) 7 (C) 8 (D) 9 7. ssuming the availability of only true input variables, the fewest number of -input open-drain NND gates that are needed to realize this function is: () 6 (B) 7 (C) 8 (D) 9 8. ssuming the availability of only true input variables, the number of pull-up resistors required to realize this function using -input open-drain NND gates is: () (B) (C) 4 (D) 5 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

3 ECE 70 Learning Outcome - - Practice Exam B The following circuit applies to questions 9 and 0: Z 9. The O set of the function realized by this circuit is: (),,Z(,4) (B),,Z(,6) (C),,Z(0,,,4,5,7) (D),,Z(0,,,5,6,7) 0. The cost of a minimal product of sums realization of this function (assuming both true and complemented variables are available) would be: () 0 (B) (C) (D) The following circuit applies to question : VCC LED 4. The ON set realized by this circuit, where the LED on condition corresponds to (,,Z)=, is: (),,Z (,4,5) (B),,Z (0,,,6,7) (C),,Z (0,,) (D),,Z (6.7) 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

4 ECE 70 Learning Outcome Practice Exam B The following circuit applies to questions and : VCC Z 4 5 OD 6 OD W Z OD W OD. Expressed in minimum sum-of-products form, the function realized by this circuit is: () W + Z (B) W + Z (C) + Z + W Z + W (D) W + Z + Z. Expressed in minimum product-of-sums form, the function realized by this circuit is: () (W+) (+Z) (B) (W + ) ( +Z ) (C) (+) (+Z) (W+Z) (W+) (D) ( + ) ( +Z ) (W +Z ) (W + ) 4. The multiplexer circuit shown realizes the following O set: (),,Z (0,,4,7) (B),,Z (0,,6,7) (C),,Z (,,4,7) (D),,Z (,,5,6) 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

5 ECE 70 Learning Outcome Practice Exam B The following circuit and timing chart apply to questions 5 and 6. ssume each gate has a propagation delay of 0 ns; use the chart provided as a worksheet. B C D 0 ns B C D (,) 5. Steady-state (static) analysis of the function realized by this circuit for the inputs provided predicts that the output (,) should: () always be low (B) always be high (C) be equal to the input (D) be equal to the input 6. Dynamic analysis of the output (,) reveals that: () a static 0 hazard will be produced whenever the inputs and transition simultaneously (B) a static hazard will be produced whenever the inputs and transition simultaneously (C) a static 0 hazard will be produced only when input transitions from low-tohigh and input transitions from high-to-low (D) a static hazard will be produced only when input transitions from high-tolow and input transitions from low-to-high 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

ECE 70 Learning Outcome - 6 - Practice Exam B The isplever-generated Reports below apply to questions 7 through 9.

6 ECE 70 Learning Outcome Practice Exam B The isplever-generated Reports below apply to questions 7 through 9. REDUCED EQUTION REPORT: P-Terms an-in an-out Type Name (attributes) /4 4 Pin /4 4 Pin ========= 7/8 Best P-Term Total: 7 Total Pins: 6 Total Nodes: 0 verage P-Term/Output: Positive-Polarity Equations: =!B&!D&&!C # B&D&&!C #!B&!D&!&C # B&D&!&C; = B&D #!&!C # &C; Reverse-Polarity Equations:! = B&!D #!B&D #!&!C # &C;! =!D&&!C #!B&&!C #!D&!&C #!B&!&C; CHIP REPORT: = B&D&!&C #!B&!D&!&C # B&D&&!C #!B&!D&&!C; = B&D # &C #!&!C; PV0G \ / \ / Vcc B C D GND ` ' 7. The total number of P terms used by this Verilog program is: () (B) 4 (C) 7 (D) 8 (E) none of these 8. The chip report indicates that the fitter program chose the following forms of the reduced equations to burn into the PLD: () the positive polarity forms of both and (B) the reverse polarity forms of both and (C) the positive polarity form of and the reverse polarity form of (D) the reverse polarity form of and the positive polarity form of 9. possible Verilog source form of the equation for is: () = (B ^ D) & ( ~^ C); (B) = (B ^ D) ( ~^ C); (C) = (B ~^ D) & ( ^ C); (D) = (B ~^ D) ( ^ C); 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

7 ECE 70 Learning Outcome Practice Exam B The Macrocell Reference igure below applies to questions 0 through. E... I0 G 0 D 0 0 OE pin OE pin I0 0 G B I I0 D0 D D D I/O pin I/O Pin C C Input pin 7 Input Pin Input pin 0 Input Pin 0 0. The possibilities for controlling the tri-state buffer enable do not include: () always O (B) always ON (C) controlled by an expression comprised of one product term (D) controlled by an expression comprised of two product terms. If D=0 and E=, the maximum number of product terms that can be utilized by a function realized by the macrocell I/O pin is: () (B) 4 (C) 5 (D) 6 (E) none of these. To realize the positive polarity equation of a function with an active low output, the following settings should be used: () C=0, B=0, = (B) C=0, B=, =0 (C) C=, B=0, = (D) C=, B=, =0 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

8 ECE 70 Learning Outcome Practice Exam B The following Verilog program applies to questions through 5:. The number of equations generated by this program is: () (B) 4 (C) 8 (D) 6 4. When TEN is negated, S[]=, and S[0]=, the outputs _z[:0] will: () all be zero (B) all be one (C) all be Hi Z (D) be equal to the inputs [:0] 5. When TEN is asserted, S[]=, and S[0]=0, the outputs _z[:0] will: () be equal to the inputs [:0] (B) be equal to the inputs B[:0] (C) be equal to the inputs C[:0] (D) be equal to the inputs D[:0] /* Mid-Size Multiplexer */ module midmux(ten,s,,b,c,d,_z); input wire TEN; input wire [:0] S; input wire [:0], B, C, D; output tri [:0] _z; wire [:0] ; assign _z = TEN? : 4'bZZZZ; (S) begin = 4 b0000; case (S) d0: = ; d: = B; d: = C; d: = D; endcase end endmodule The following Verilog program applies to questions 6 and 7: 6. If input I[0] is asserted and all the other inputs are negated, the output produced will be: () E_z[]=0, E_z[0]=0, G=0 (B) E_z[]=0, E_z[0]=0, G= (C) E_z[]=Hi Z, E_z[0]=Hi Z, G=Hi Z (D) E_z[]=Hi Z, E_z[0]=Hi Z, G= 7. If inputs I[], I[], and TEN are asserted and all the other inputs are negated, the output produced will be: () E_z[]=0, E_z[0]=0, G=0 (B) E_z[]=0, E_z[0]=, G= (C) E_z[]=, E_z[0]=0, G= (D) E_z[]=Hi Z, E_z[0]=Hi Z, G= /* Mid-Size Priority Encoder */ module prienc(i, E_z, G, TEN); input wire [:0] I; input wire TEN; output tri [:0] E_z; output wire G; reg [:0] EG; (I) begin casez (I) 4'b0000: EG = 'b000; 4'b000: EG = 'b00; 4'b00?: EG = 'b0; 4'b0??: EG = 'b0; 4'b???: EG = 'b; endcase end assign G = EG[0]; assign E_z = TEN? EG[:] : 'bzz; endmodule 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

ECE 70 Learning Outcome - 9 - Practice Exam B The following Verilog program and V0 diagram apply to questions 8 through 0.

Just when you thought the exam was safe from your well-intentioned best friend from another major (BM), you discover a Verilog program they have written for a V0.

The number of product terms required to realize the equation for BOUT, given the Verilog program as written, is: () 4 (B) 04 (C) 048 (D) 4096 (E) none of these Pins 4 & 8 P-terms each Pins 5 & 0

9 ECE 70 Learning Outcome Practice Exam B The following Verilog program and V0 diagram apply to questions 8 through 0. /* Big OR ttempt on V0 */ module bigxor (I, BOUT); input wire [:0] I; output wire BOUT; assign BOUT = ^I; endmodule 8. Just when you thought the exam was safe from your well-intentioned best friend from another major (BM), you discover a Verilog program they have written for a V0. It looks like this time your BM is attempting to create a -variable OR function. The number of product terms required to realize the equation for BOUT, given the Verilog program as written, is: () 4 (B) 04 (C) 048 (D) 4096 (E) none of these Pins 4 & 8 P-terms each Pins 5 & 0 P-terms each Pins 6 & P-terms each Pins 7 & 0 4 P-terms each Pins 8 & 9 6 P-terms each 9. s expected, the Verilog program targeting a V0 doesn t fit (as written) because: () the pin numbers are not specified (B) there are an insufficient number of input pins (C) there are an insufficient number of I/O (macrocell) pins (D) there are an insufficient number of P-terms 0. The Verilog program shown could be modified to successfully realize the Big OR function on a single V0 by: () adding an explicit pin assignment for BOUT (B) adding explicit pin assignments for all the input and output variables (C) splitting the equation for BOUT into two 5-variable OR functions (assigned to two specific macrocells), the outputs of which could then be ORed with the other two inputs using a third macrocell (i.e. using a total of macrocells) (D) changing their degree option, as there is no way to implement a -variable OR function on a V0, and consequently there is no way to successfully modify the Verilog program! 09 by D. G. Meyer / Purdue University may not be copied or reproduced, in any form or by any means.

Lecture Summary Module 2 Combinational Logic Circuits

Lecture Summary Module 2 Combinational Logic Circuits Learning Outcome: an ability to analyze and design combinational logic circuits Learning Objectives: 2-1. identify minterms (product terms) and maxterms