AN Mbit RHQDRII+ FIFO Interface Controller. Abstract. Introduction. RHQDRII+ Based FIFO

Transcription

1 Abstract 72Mbit RHRII+ FIFO Interface Controller AN84534 Authors: Suhail Zain, Karthik Navalpakam Associated Part Family: CYRS154*AV18 This application note describes the architecture and timing details of a FIFO implementation based on Cypress s Radiation Hardened R II+ SRAMs. The accompanying synthesizable reference design targets Xilinx Virtex-5V family of FPGA devices for an Industry Standard FIFO realization. Introduction FIFO is an acronym for First In, First Out. It is a memory queue providing in-order storage and retrieval. FIFO memory allows data to be written into and read out from its array at independent data rates. FIFOs are ubiquitous constructs needed for data manipulation tasks such as clock domain crossing and low latency memory buffering. Monitoring the status of the FIFO memory is critical to avoiding any data under or over flows and is achieved by the Full and mpty flags. As the name applies, Full flag is asserted when FIFO is full. Similarly, mpty flag is high when FIFO is empty. Figure 1 shows a functional block description of a typical FIFO memory. atain WNb WCLK WCSb Write Control Write Pointer Input Register ual Port RAM Array Read Control Read Pointer RNb RCLK RCSb Pop=1 C Count Count = Count < Max State (1) mpty State (5) Push (not full) FIFO State Machine Pop = 1 C Count Count = Count < Max Pop = 1 Pop C Count Count Count > Pop =1 C Count State (2) Full State (4) Pop (not empty) Figure 2: FIFO State Machine Count = Max Pop = 1 C Count Count > Count = Max Another important set of FLAGs generally implemented (but not required) is Almost Full & Almost mpty. These are used by the system logic to either stop sending (PUSH) or stop receiving (POP) data to ensure data in transit can be properly handled. A value less than the maximum count for Almost Full and a value greater than zero for Almost mpty can be used to generate these flags respectively. FIFO Functional Block iagram Output Register ataout FIFO Control Logic Figure 1: FIFO Functional Block iagram Full mpty Read_RR Write_RR Ob RHRII+ Based FIFO Implementing a FIFO using 72Mbit RHRII+ means replacing the ual Port RAM in figure 1 with 72Mbit RHRII+. However, 72Mbit RHRII+ is a Single Port memory with separate read and write buses, each employing double data rate architecture. Thus, forming FIFO functionality will require extra logic. Figure 3 shows the basic RHRII+ (x18) functional block description. Figure 2 shows the FIFO state machine logic which controls the Read and Write pointers along with maintaining correct FLAG logic. March 1, 213 ocument. TB 1

2 AN_SZZX4 RPSb Address[21:] RHRII+ Architecture te: The Physical layer components are pre-built into the Virtex5V architecture. ata[17:] K WPSb C [17:] Clock Generator Write Control Logic W R I T C O R Address Register Write Registers 36 Megabit Array (2Mbit X 18) Read Registers Write Registers 36 Megabit Array (2Mbit X 18) R A C O R 18 Read Control Logic RG RG RG Figure 3: RHRII+ Function Block iagram Figure 4 shows the functional block diagram of a FIFO controller based on Xilinx s Virtex5V platform. sys_clk sys_rst_in fifo_dwl/h wclk fifo_w_en_n fifo_full_n fifo_afull_n fifo_empty_n fifo_aempty_n fifo_r_en_n rclk fifo_qrl/h datain(a) wclk(a) wren(a) wadd(a) port_w_addr port_w_en port_w_clk reset full almost_full empty almost_empty port_r_clk port_r_en port_r_addr radd(a) ren(a) rclk(a) dataout(a) BRAM (1KX36) FIFO Controller BRAM (1KX36) d_to_qdr(b) sclk(b) ren(b) radd(b) qdr_wb_addr qdr_wb_ren qdr_addr wadd(b) wen(b) sclk(b) d_fm_qdr(b) Xilinx Virtex5V Based FIFO Controller qdr_wen qdr_ren master_clk qdr_rb_wen qdr_rb_addr Reset W AR W_N R_N R RHRII+ Controller State Machine Calibration Read Write Control AC Logic 72Mbit Radiation Hardened FIFO Physical Layer Read/Write data following RII+ protocol RHRII+ Controller Read/Write Requests with correct timing FIFO Controller FIFO functionality Master_Clock Write_data Address Read_data System Clock Write ata Address CLKIN Read ata Physical Layer CLK PLL / LL CLK9 Vdd CLK PLL / LL Figure 4: Virtex6V based FIFO Controller etailed description of each block is as follows: Physical Layer The Physical layer transmits and receives all the signals and data to and from the 72Mbit RHRII+ memory. It performs the following main functions: CLK9 CLKIN Clock (K) Write ata cho Clock (C) Write data into RHRII+ Read data from RHRII+ Provide all the necessary control signals Transfers Read as well as write data clock domain from the RHRII+ domain to FPGA domain The ouble ata Rate (R) registers shown ensure data can be sent and received on both edges of the clock. Moreover, the LLs center-align the data for writing and echo clocks for reading to ensure optimum data valid window capture. WPSb RPSb Read ata qdr_k qdr_d qdr_w_n qdr_r_n qdr_cq qdr_q RHRII+ Controller The RHRII+ Controller provides an easy-to-use interface between the FIFO controller and the Physical layer. The main function of the controller is to ensure that data and timing are aligned with the RHRII+ specifications. etails are as follows: The read and write requests from the FPGA User logic are turned into RHRII+ SRAM read and write requests with correct timing (R) rror etection and Correction (SC) Synchronization and training sequences Phased clock generation and datapath sequencing etails on the RHRII+ controller can be found in application notes AN_SZZX3 and AN6972. FIFO Controller The FIFO Controller implements the FIFO functionality. It is a very simple interface employing synchronous read and write operations. This FIFO design accommodates different read and write frequencies up to the maximum specified frequency limit set by Xilinx Virtex5V. Since 72Mbit RHRII+ is a single port memory with separate read and write buses, Block RAMs are used to implement the simple dual port interface needed for FIFO. ata flow is automatic and is controlled by read and write counters in conjunction with FULL and MPTY flags. Almost FULL (A_FULL) and almost MPTY (A_MPTY) flags are also present for early warning. FIFO xternal Port escriptions Port Name irection escription sys_clk Input Master Clock Used for RHRII+ Controller & RHRII+ memory sys_clk_27 Input Master Clock with 27 Used for RHRII+ Controller clk_2 Input 2MHz clock for idelayctrl primitives sys_rst_in Input Asynchronous reset to all FIFO functions including RHRII+ Controller wclk Input Clock for write domain operation fifo_w_en_n Input Active low Write enable fifo_dwl, fifo_dwh Input ata input, synchronous to wclk fifo_full_n Output FIFO memory is full synchronous to wclk fifo_afull_n Output FIFO is almost full - synchronous to wclk rclk Input Clock for read domain operation March 1, 213 ocument. TB 2

3 fifo_r_en_n Input Active low Read enable fifo_qrl, fifo_qrh Output ata output, synchronous to rclk fifo_qrl_err, fifo_qrh_err Output ata out err status from internal AC fifo_qr_valid_n Output Active low ata out valid indicator fifo_empty_n Output FIFO is empty - synchronous to rclk fifo_aempty_n Output FIFO is almost empty - synchronous to rclk Table 1: FIFO external Port description RHRII+ Interface Port escription Port Name irection escription qdr_d Output Write ata for RHRII+ qdr_bw_n Output Byte nables for Write ata for RHRII+ qdr_q Input Read ata from RHRII+ qdr_sa Output Address for RHRII+ qdr_w_n Output Write Port nable for RHRII+ qdr_r_n Output Read Port nable for RHRII+ qdr_dll_off_n Output LL Off signal for RHRII+ qdr_k Output Master Clock for RHRII+ - True qdr_k_n Output Master Clock for RHRII+ - Complement qdr_cq Input cho Clock from RHRII+ - True qdr_cq_n Input cho Clock from RHRII+ - Complement qdr_wb_addr Output Address for write Block RAM read port (mclk) write data to RHRII+ qdr_wb_ren Output Read enable for write Block RAM (mclk) qdr_addr Output Address for RHRII+ memory (mclk) qdr_wen Output Write enable for RHRII+ memory (mclk) qdr_ren Output Read enable for RHRII+ memory (mclk) qdr_rb_addr Output Address for read Block RAM write port (mclk) read data to RHRII+ qdr_rb_wen Output Write enable for read Block RAM (mclk) Table 3: FIFO internal pin description FIFO Controller State Machine This state machine is similar to the one shown in figure 2. However, the RHRII+ FIFO controller has the additional complexity to properly transfer data between the read and writer Block RAMs and the main RHRII+ SRAM to maintain the simple dual port functionality. Figure 5 shows the flowchart for a FIFO controller supporting a simple dual port memory. The read pointer (rd_ptr) and write pointer (wr_ptr) are used as addresses and work in a round robin fashion. Only FULL and MPTY flags are implemented. MAX refers to the maximum allowable address space. Table 2: RHRII+ Interface Port escription FIFO Internal Port escription (For explanation only Actual implemented names may vary) Port Name irection escription port_w_addr Output Address for write Block RAM (wclk) port_w_en Input Write enable used to increment write address (wclk) port_w_clk Input Write port clock reset Input Asynchronous reset full Input Full flag FIFO is full (wclk) a_full Input Almost full flag FIFO is almost full (wclk) port_r_addr Output Address for read Block RAM (rclk) port_r_en Input Read enable used to increment write address (rclk) port_w_clk Input Read port clock March 1, 213 ocument. TB 3

4 Power ON / RST wr_ptr = rd_ptr = State = IL Power ON / RST r_mem = port_w_addr = port_r_addr = qdr_wb_addr = qdr_rb_addr = State = IL Reset rclk Reset wclk rclk wclk State = RA State = WRIT port_r_addr ++ port_w_addr ++ rd_ptr = wr_ptr State = MPTY FLAG MPTY = 1 wr_ptr - rd_ptr = MAX State = FULL FLAG FULL = 1 Burst 2 port_r_addr - qdr_rb_addr = 2 State = RA_R qdr_wb_addr = +2 r_mem == 1 Burst 4 port_r_addr - qdr_rb_addr = 4 State = RA_R qdr_wb_addr = +4 Burst 2 port_w_addr mod 2 State = WRIT_R port_w_addr = qdr_wb_addr {, 1} Burst 4 Port_w_addr mod 4 State = WRIT_R port_w_addr = qdr_wb_addr {,1,2,3} ren = 1 State = POP FLAG (ne) rd_ptr ++ wen = 1 State = PUSH FLAG (ne) wr_ptr ++ ata Mirroring Write Block RAM to Read Block RAM r_mem == qdr_rb_addr port_r_addr == MAX State = MIRROR_RBM qdr_rb_addr = +2 State = Read Mirror r_mem == qdr_rb_addr port_r_addr == MAX State = MIRROR_RBM qdr_rb_addr = +4 Figure 5: RHRII+ FIFO Controller Flowchart RHRII+ implemented as a simple dual port requires two Block RAMs where data coherence management is required. Write: For the write Block RAM, as soon as data is available, a write command to the RHRII+ controller is issued. port_w_addr address pointer is incremented upon each write cycle and the corresponding qdr_wb_addr is used to read data from the write Block RAM and write data into the RHRII+. Read: For the read Block RAM, RHRII+ latency needs to be mitigated (controller and RHRII+). The FIFO controller will maintain a copy of the data in the read Block RAM. As long as the read Block RAM has storage space, data written into the write Block RAM will be mirrored into the read Block RAM. Once the read Block RAM gets full, every following read (POP) command will initiate a read command to the RHRII+ controller to bring data from the RHRII+ memory. port_r_addr address pointer is incremented on each read cycle and the corresponding qdr_rb_addr is used to write data from the RHRII+ into the read Block RAM. port_r_addr and qdr_rb_addr work in a round robin fashion. r_mem = 1 (full) MAX = Size of the Read Block RAM r_mem = Read Block RAM mpty/full Flag Figure 6: ual Port to RHRII+ Interface Flowchart RHRII+ FIFO Benefits The 72Mbit RHRII+ based FIFO is an exceptionally deep and extremely high speed FIFO memory. Key user benefits are as follows: High density offering (72Mbit) X18 or X36 configurations 25MHz maximum performance on both read and write ports Built-in AC (SC) RHRII+ FIFO Timing Waveforms Basic Read & Write Figure 6 provides a flowchart for implementing dual port interface for RHRII+. March 1, 213 ocument. TB 4

5 FIFO Read & Write A B C F FLAG Name Latency wclk rclk fifo_w_en_n fifo_r_en_n fifo_dwl/h fifo_qrl/h Figure 7: FIFO Read & Write Full FLAG Assertion/esertion wclk fifo_w_en_n fifo_dwl[71:] fifo_dwh[71:] LAS3 LAST-2 Full Flag, Almost Full Flag Assertion / easssertion Write Cycle, A assertion 1 1 LAST-1 LAST fifo_full_n and fifo_afull_n has one clock latency. fifo_afull_n: when asserted, indicates one more write is allowed before FIFO is full mpty Flag assertion with read (# of Clock Cycles) Almost mpty Flag assertion with read mpty Flag desertion with write 14 Almost mpty Flag desertion with write 14 Full Flag assertion with write 1 Almost Full Flag assertion with write 1 Full Flag desertion with read 4 Almost Full Flag desertion with read 4 fifo_full_n fifo_afull_n Read Cycle, A de-assertion rclk fifo_r_en_n fifo_qrl[71:] 2 fifo_qrh[71:] fifo_qr_valid fifo_full_n 1 3 fifo_afull_n Figure 8: Full FLAG Assertion/esertion mpty FLAG Generation mpty Flag, Almost mpty Flag Assertion / easssertion Write Cycle F, AF deassertion wclk fifo_w_en_n fifo_dwl[71:] 2 fifo_dwh[71:] 1 3 fifo_empty_n fifo_aempty_n Read Cycle F, AF assertion t valid read rclk fifo_aempty_n: when fifo_r_en_n asserted, indicates only one more read is allowed before FIFO Fifo_qrl[71:] LAST-9 LAST-7 LAST-5 LAST-3 LAST-1 becomes empty fifo_qrh[71:] LAST-8 LAST-6 LAST-4 LAST-2 LAST fifo_qr_valid_n fifo_empty_n fifo_aempty_n. Figure 9: mpty FLAG Assertion/esertion FLAG Latencies March 1, 213 ocument. TB 5

6 Specifications Table 4: evice Utilization SPC I# PARAM SCRIPTION UNITS 1 Slices Configurable Logic Blocks GCLK Buffers Clocks 5 3 Block RAMs Memory Blocks 4 March 1, 213 ocument. TB 6

7 Reference esign Summary Table 5: Reference esign Matrix Parameter escription eveloper Name Target evices Xilinx Corporation Cypress Semiconductor Virtex-5V FPGA Source Code Provided Source Code Format Verilog Functional Simulation Performed Timing Simulation Performed Testbench Provided Simulator ModelSim Hardware Verified March 1, 213 ocument. TB 7

8 Summary The application note describes the implementation of a FIFO Controller for either a two-word or a four-word burst RHRII+ SRAM memories based on Xilinx s Virtex-5V FPGA. The reference design utilizes built-in Virtex-5V structures to provide a high performance solution. March 1, 213 ocument. TB 8

9 ocument History ocument Title: 72Mbit RHR II+ FIFO Interface Controller ocument Number: Revision CN Orig. of Change Submission ate ** SZZX New Spec. escription of Change ocument subject-specific trademark information, if any. xample - PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC esigner, and PSoC xpress are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. The blue bar and the information below it are placed at the bottom portion of the page. Cypress Semiconductor 198 Champion Court San Jose, CA Phone: Fax: Cypress Semiconductor Corporation, 28. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. r does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. isclaimer: CYPRSS MAKS NO WARRANTY OF ANY KIN, XPRSS OR IMPLI, WITH RGAR TO THIS MATRIAL, INCLUING, BUT NOT LIMIT TO, TH IMPLI WARRANTIS OF MRCHANTABILITY AN FITNSS FOR A PARTICULAR PURPOS. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. March 1, 213 ocument. TB 9