Project: Visual Cache Simulator Input: Real Addresses Outputs: 1. Number of Hits 2. Number of Misses 3. Hit Ratio 4. Visual Representation of Cache

Size: px
Start display at page:

Download "Project: Visual Cache Simulator Input: Real Addresses Outputs: 1. Number of Hits 2. Number of Misses 3. Hit Ratio 4. Visual Representation of Cache"

Transcription

1 Project: Visual Cache Simulator Input: Real Addresses Outputs: 1. Number of Hits 2. Number of Misses 3. Hit Ratio 4. Visual Representation of Cache including 4.1. Index or Index Set 4.2. Tag 4.3. Cache Organizations to be Simulated: 1. Direct-Mapped Cache 2. Cache 3. Cache Replacement Policies: 1. Least Recently Used () 2. First-In First-Out 3. Random

2 Prototype Display 1. Direct-Mapped Cache Address Tag Index Byte Byte Byte Byte Byte Tag Index Hits Hit Ratio Misses Replacement Policy None FIFO Random Cache Organization Next Address Direct Figure 1. Direct-Mapped Cache Display

3 Direct-Mapped Cache Operation: 1.1 Cache Organization drop-down list. The Cache Organization drop-down list is used to select a Direct-Mapped Cache Simulation. 1.2 Replacement Policy drop-down list. The Replacement Policy drop-down list does not function and None is displayed as the option selected since a Direct-Mapped Cache has only a single option for replacement. The new data and address for a particular index replace the tag and data stored in the cache if the new tag is different from the tag stored in the cache. 1.3 Next Address button. The Next Address button is used to solicit a new address and data. The new address and data are displayed in the Address and boxes. The address is divided into three parts, tag, index, and byte as shown. The address is displayed in binary. are represented in hexadecimal. 1.4 Cache display. The cache is displayed as three columns where each column has as many rows as there are index values. Since the index shown in this example has three (3) bits, there are eight (8) rows. The columns are labeled Tag, Index, and respectively. Each time a new address is generated the index row where the tag and data are stored is highlighted. Two levels of highlighting are used. A bright highlight is employed if the tag and data are replacing an existing tag and data. A lesser highlight is employed if the tag and data are found in the cache. Initially all tags and data are blank. Tags are displayed in binary. are displayed in hexadecimal. Index values are fixed as labels for each row. 1.5 Hit box. The hit box records the number of times that address is found in the cache. 1.6 Miss box. The miss box records the number of times the address cannot be found in the cache. 1.7 Hit Ratio box. The ratio box records the fraction found by dividing the number of hits by the total number of addresses. 1.8 Address box. The address box displays the three components of the address, tag, index, and byte for each new address generated. 1.9 box. The data box displays the contents of the address given in the Address box. Eight hexadecimal digits are displayed.

4 2 Cache Address Tag Byte Byte Byte Byte Byte Tag Hits Hit Ratio Misses Replacement Policy FIFO Random Next Address Cache Organization Direct Figure 2. Cache Display 2.1 Cache Organization drop-down list. The Cache Organization drop-down list is used to select a Fully Associative Cache Simulation. 2.2 Replacement Policy drop-down list. The Replacement Policy drop-down list permits one of three selections:, FIFO, or Random. When is selected the cache replaces the least recently used tag and data in the event of a cache miss. When FIFO is selected the cache replaces the oldest tag

5 and data in the cache in the event of a cache miss. When Random is selected the cache random selects a tag and data to replace on a cache miss. 2.3 Next Address button. The Next Address button is used to solicit a new address and data. The new address and data are displayed in the Address and boxes. The address is divided into three parts, tag, index, and byte as shown. The address is displayed in binary. are represented in hexadecimal. 2.4 Cache display. The cache is displayed as two columns where each column has as many rows as there are index values in the direct-mapped cache. Since the index in the direct-mapped cache has three (3) bits, there are eight (8) rows. The columns are labeled Tag and respectively. Each time a new address is generated the row where the tag and data are stored is highlighted. Three levels of highlighting are used. A bright highlight is employed if the tag and data are replacing an existing tag and data. A middle highlight is employed if the tag and data are found in the cache. A lesser highlight is used to identify the next tag and data to be replaced in the event of a cache miss. Initially all tags and data are blank. Tags are displayed in binary. are displayed in hexadecimal. 2.5 Hit box. The hit box records the number of times that address is found in the cache. 2.6 Miss box. The miss box records the number of times the address cannot be found in the cache. 2.7 Hit Ratio box. The ratio box records the fraction found by dividing the number of hits by the total number of addresses. 2.8 Address box. The address box displays the three components of the address, tag, index, and byte for each new address generated. 2.9 box. The data box displays the contents of the address given in the Address box. Eight hexadecimal digits are displayed.

6 3 Cache Address Tag Index Byte Byte Byte Byte Byte Index Tag Tag Hits Hit Ratio Misses Replacement Policy FIFO Random Next Address Cache Organization Direct Figure 3. Cache Display 3.1 Cache Organization drop-down list. The Cache Organization drop-down list is used to select a Set Associative Cache Simulation. 3.2 Replacement Policy drop-down list. The Replacement Policy drop-down list permits one of three selections:, FIFO, or Random. When is selected the cache replaces the least recently used tag and data in the event of a cache miss. When FIFO is selected the cache replaces the oldest tag

7 and data in the cache in the event of a cache miss. When Random is selected the cache random selects a tag and data to replace on a cache miss. 3.3 Next Address button. The Next Address button is used to solicit a new address and data. The new address and data are displayed in the Address and boxes. The address is divided into three parts, tag, index, and byte as shown. The address is displayed in binary. are represented in hexadecimal. 3.4 Cache display. The cache is displayed as five columns where each column has half as many rows as there are index values in the direct-mapped cache. Since the index in the direct-mapped cache has three (3) bits, there are eight (8) rows in the direct-mapped cache and four (4) rows in the set associative cache. The columns are labeled Index, Tag,, Tag, and respectively. Tags are displayed in binary. are displayed in hexadecimal. Index values are fixed as labels for each row. Each row is a set. The replacement policy is applied to each set. Highlighting is employed to identify the following The tag and data in the cache corresponding to the current address and data shown in the address and data boxes are given a middle highlight value. The cache tag and data that are replaced are given the brightest highlight. In every set the next tag and address to be replaced is highlighted using the lowest level highlight. 3.5 Hit box. The hit box records the number of times that address is found in the cache. 3.6 Miss box. The miss box records the number of times the address cannot be found in the cache. 3.7 Hit Ratio box. The ratio box records the fraction found by dividing the number of hits by the total number of addresses. 3.8 Address box. The address box displays the three components of the address, tag, index, and byte for each new address generated. 3.9 box. The data box displays the contents of the address given in the Address box. Eight hexadecimal digits are displayed.

Figure 1: Organisation for 128KB Direct Mapped Cache with 16-word Block Size and Word Addressable

Figure 1: Organisation for 128KB Direct Mapped Cache with 16-word Block Size and Word Addressable Tutorial 12: Cache Problem 1: Direct Mapped Cache Consider a 128KB of data in a direct-mapped cache with 16 word blocks. Determine the size of the tag, index and offset fields if a 32-bit architecture

More information

ECE331 Homework 4. Due Monday, August 13, 2018 (via Moodle)

ECE331 Homework 4. Due Monday, August 13, 2018 (via Moodle) ECE331 Homework 4 Due Monday, August 13, 2018 (via Moodle) 1. Below is a list of 32-bit memory address references, given as hexadecimal byte addresses. The memory accesses are all reads and they occur

More information

Memory memories memory

Memory memories memory Memory Organization Memory Hierarchy Memory is used for storing programs and data that are required to perform a specific task. For CPU to operate at its maximum speed, it required an uninterrupted and

More information

Chapter Seven. Large & Fast: Exploring Memory Hierarchy

Chapter Seven. Large & Fast: Exploring Memory Hierarchy Chapter Seven Large & Fast: Exploring Memory Hierarchy 1 Memories: Review SRAM (Static Random Access Memory): value is stored on a pair of inverting gates very fast but takes up more space than DRAM DRAM

More information

Structure of Computer Systems

Structure of Computer Systems 222 Structure of Computer Systems Figure 4.64 shows how a page directory can be used to map linear addresses to 4-MB pages. The entries in the page directory point to page tables, and the entries in a

More information

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Comp 411 Computer Organization Fall 2006 Solutions Problem Set #10 Problem 1. Cache accounting The diagram below illustrates a blocked, direct-mapped cache

More information

CMU Introduction to Computer Architecture, Spring 2014 HW 5: Virtual Memory, Caching and Main Memory

CMU Introduction to Computer Architecture, Spring 2014 HW 5: Virtual Memory, Caching and Main Memory CMU 18-447 Introduction to Computer Architecture, Spring 2014 HW 5: Virtual Memory, Caching and Main Memory Instructor: Prof. Onur Mutlu TAs: Rachata Ausavarungnirun, Varun Kohli, Xiao Bo Zhao, Paraj Tyle

More information

Day 4 Percentiles and Box and Whisker.notebook. April 20, 2018

Day 4 Percentiles and Box and Whisker.notebook. April 20, 2018 Day 4 Box & Whisker Plots and Percentiles In a previous lesson, we learned that the median divides a set a data into 2 equal parts. Sometimes it is necessary to divide the data into smaller more precise

More information

Com S 321 Problem Set 3

Com S 321 Problem Set 3 Com S 321 Problem Set 3 1. A computer has a main memory of size 8M words and a cache size of 64K words. (a) Give the address format for a direct mapped cache with a block size of 32 words. (b) Give the

More information

Full Name: CS Account:

Full Name: CS Account: THE UNIVERSITY OF BRITISH COLUMBIA CPSC 313: QUIZ 4 October 31, 2018 Full Name: CS Account: Signature: UBC Student #: Important notes about this examination 1. Write your 4 or 5 character CS account both

More information

Chapter 6 Memory 11/3/2015. Chapter 6 Objectives. 6.2 Types of Memory. 6.1 Introduction

Chapter 6 Memory 11/3/2015. Chapter 6 Objectives. 6.2 Types of Memory. 6.1 Introduction Chapter 6 Objectives Chapter 6 Memory Master the concepts of hierarchical memory organization. Understand how each level of memory contributes to system performance, and how the performance is measured.

More information

CSE 410 Computer Systems. Hal Perkins Spring 2010 Lecture 12 More About Caches

CSE 410 Computer Systems. Hal Perkins Spring 2010 Lecture 12 More About Caches CSE 4 Computer Systems Hal Perkins Spring Lecture More About Caches Reading Computer Organization and Design Section 5. Introduction Section 5. Basics of Caches Section 5. Measuring and Improving Cache

More information

CHAPTER 6 Memory. CMPS375 Class Notes (Chap06) Page 1 / 20 Dr. Kuo-pao Yang

CHAPTER 6 Memory. CMPS375 Class Notes (Chap06) Page 1 / 20 Dr. Kuo-pao Yang CHAPTER 6 Memory 6.1 Memory 341 6.2 Types of Memory 341 6.3 The Memory Hierarchy 343 6.3.1 Locality of Reference 346 6.4 Cache Memory 347 6.4.1 Cache Mapping Schemes 349 6.4.2 Replacement Policies 365

More information

ECE Lab 8. Logic Design for a Direct-Mapped Cache. To understand the function and design of a direct-mapped memory cache.

ECE Lab 8. Logic Design for a Direct-Mapped Cache. To understand the function and design of a direct-mapped memory cache. ECE 201 - Lab 8 Logic Design for a Direct-Mapped Cache PURPOSE To understand the function and design of a direct-mapped memory cache. EQUIPMENT Simulation Software REQUIREMENTS Electronic copy of your

More information

ECEC 355: Cache Design

ECEC 355: Cache Design ECEC 355: Cache Design November 28, 2007 Terminology Let us first define some general terms applicable to caches. Cache block or line. The minimum unit of information (in bytes) that can be either present

More information

CS 433 Homework 5. Assigned on 11/7/2017 Due in class on 11/30/2017

CS 433 Homework 5. Assigned on 11/7/2017 Due in class on 11/30/2017 CS 433 Homework 5 Assigned on 11/7/2017 Due in class on 11/30/2017 Instructions: 1. Please write your name and NetID clearly on the first page. 2. Refer to the course fact sheet for policies on collaboration.

More information

Locality and Data Accesses video is wrong one notes when video is correct

Locality and Data Accesses video is wrong one notes when video is correct Cache Review This lesson is a review of caches. Beginning with the structure of the cache itself, including set associative and direct mapped caches. Then the lesson discusses replacement policies, specifically

More information

Virtual Memory Worksheet

Virtual Memory Worksheet Virtual Memory Worksheet (v + p) bits in virtual address (m + p) bits in physical address 2 v number of virtual pages 2 m number of physical pages 2 p bytes per physical page 2 v+p bytes in virtual memory

More information

Lecture 12: Memory hierarchy & caches

Lecture 12: Memory hierarchy & caches Lecture 12: Memory hierarchy & caches A modern memory subsystem combines fast small memory, slower larger memories This lecture looks at why and how Focus today mostly on electronic memories. Next lecture

More information

Why memory hierarchy

Why memory hierarchy Why memory hierarchy (3 rd Ed: p.468-487, 4 th Ed: p. 452-470) users want unlimited fast memory fast memory expensive, slow memory cheap cache: small, fast memory near CPU large, slow memory (main memory,

More information

CHAPTER 6 Memory. CMPS375 Class Notes Page 1/ 16 by Kuo-pao Yang

CHAPTER 6 Memory. CMPS375 Class Notes Page 1/ 16 by Kuo-pao Yang CHAPTER 6 Memory 6.1 Memory 233 6.2 Types of Memory 233 6.3 The Memory Hierarchy 235 6.3.1 Locality of Reference 237 6.4 Cache Memory 237 6.4.1 Cache Mapping Schemes 239 6.4.2 Replacement Policies 247

More information

Problem 9. VM address translation. (9 points): The following problem concerns the way virtual addresses are translated into physical addresses.

Problem 9. VM address translation. (9 points): The following problem concerns the way virtual addresses are translated into physical addresses. Problem 9. VM address translation. (9 points): The following problem concerns the way virtual addresses are translated into physical addresses. The memory is byte addressable. Memory accesses are to 1-byte

More information

Tutorial for Chapter 3, 4

Tutorial for Chapter 3, 4 Eastern Mediterranean University School of Computing and Technology ITEC2 Computer Organization & Architecture Tutorial for Chapter 3, 4 Number Systems Binary Number Systems o Base = 2 o A single bit can

More information

administrivia talking about caches today including another in class worksheet

administrivia talking about caches today including another in class worksheet administrivia talking about caches today including another in class worksheet 1 memory hierarchy working on memory hierarchy now ranges from small and fast (registers) through big and almost fast (RAM)

More information

Administrivia. Expect new HW out today (functions in assembly!)

Administrivia. Expect new HW out today (functions in assembly!) Caching 1/25/19 Administrivia Expect new HW out today (functions in assembly!) Memory so far Big array indexed by the memory address accessed by load and store of various types Implicitly assumed: One

More information

Registers. Instruction Memory A L U. Data Memory C O N T R O L M U X A D D A D D. Sh L 2 M U X. Sign Ext M U X ALU CTL INSTRUCTION FETCH

Registers. Instruction Memory A L U. Data Memory C O N T R O L M U X A D D A D D. Sh L 2 M U X. Sign Ext M U X ALU CTL INSTRUCTION FETCH PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U X C O T R O L ALU CTL ISTRUCTIO FETCH ISTR DECODE REG FETCH EXECUTE/ ADDRESS CALC MEMOR ACCESS WRITE BACK A D D A D D A L U

More information

Birkbeck (University of London) Department of Computer Science and Information Systems. Introduction to Computer Systems (BUCI008H4)

Birkbeck (University of London) Department of Computer Science and Information Systems. Introduction to Computer Systems (BUCI008H4) Birkbeck (University of London) Department of Computer Science and Information Systems Introduction to Computer Systems (BUCI008H4) CREDIT VALUE: none Spring 2017 Mock Examination Date: Tuesday 14th March

More information

ECE 3055: Final Exam

ECE 3055: Final Exam ECE 3055: Final Exam Instructions: You have 2 hours and 50 minutes to complete this quiz. The quiz is closed book and closed notes, except for one 8.5 x 11 sheet. No calculators are allowed. Multiple Choice

More information

Virtual Memory Overview

Virtual Memory Overview Virtual Memory Overview Virtual address (VA): What your program uses Virtual Page Number Page Offset Physical address (PA): What actually determines where in memory to go Physical Page Number Page Offset

More information

Number System. Introduction. Decimal Numbers

Number System. Introduction. Decimal Numbers Number System Introduction Number systems provide the basis for all operations in information processing systems. In a number system the information is divided into a group of symbols; for example, 26

More information

Review: Computer Organization

Review: Computer Organization Review: Computer Organization Cache Chansu Yu Caches: The Basic Idea A smaller set of storage locations storing a subset of information from a larger set. Typically, SRAM for DRAM main memory: Processor

More information

ELCT 707 Micro Computer Applications Final-term Exam, Winter 2009

ELCT 707 Micro Computer Applications Final-term Exam, Winter 2009 German University in Cairo Jan 16 th 2010 Information Engineering and Technology Dept. Dr. Gamal Fahmy Bar Code ELCT 707 Micro Computer Applications Final-term Exam, Winter 2009 Exam Duration: Three hours

More information

Memory hierarchy and cache

Memory hierarchy and cache Memory hierarchy and cache QUIZ EASY 1). What is used to design Cache? a). SRAM b). DRAM c). Blend of both d). None. 2). What is the Hierarchy of memory? a). Processor, Registers, Cache, Tape, Main memory,

More information

CS152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Spring Caches and the Memory Hierarchy

CS152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Spring Caches and the Memory Hierarchy CS152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Spring 2019 Caches and the Memory Hierarchy Assigned February 13 Problem Set #2 Due Wed, February 27 http://inst.eecs.berkeley.edu/~cs152/sp19

More information

UW CSE 351, Winter 2013 Final Exam

UW CSE 351, Winter 2013 Final Exam Full Name: Student ID #: UW CSE 351, Winter 2013 Final Exam March 20, 2013 2:30pm - 4:20pm Instructions: Write your full name and UW student ID number on the front of the exam. When the exam begins, make

More information

CS152 Computer Architecture and Engineering

CS152 Computer Architecture and Engineering CS152 Computer Architecture and Engineering Caches and the Memory Hierarchy Assigned 9/17/2016 Problem Set #2 Due Tue, Oct 4 http://inst.eecs.berkeley.edu/~cs152/fa16 The problem sets are intended to help

More information

JNTUWORLD. 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15]

JNTUWORLD. 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15] Code No: 09A50402 R09 Set No. 2 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15] 2. (a) Discuss asynchronous serial transfer concept? (b) Explain in

More information

ECE 2300 Digital Logic & Computer Organization. More Caches

ECE 2300 Digital Logic & Computer Organization. More Caches ECE 23 Digital Logic & Computer Organization Spring 218 More Caches 1 Announcements Prelim 2 stats High: 79.5 (out of 8), Mean: 65.9, Median: 68 Prelab 5(C) deadline extended to Saturday 3pm No further

More information

WEEK 7. Chapter 4. Cache Memory Pearson Education, Inc., Hoboken, NJ. All rights reserved.

WEEK 7. Chapter 4. Cache Memory Pearson Education, Inc., Hoboken, NJ. All rights reserved. WEEK 7 + Chapter 4 Cache Memory Location Internal (e.g. processor registers, cache, main memory) External (e.g. optical disks, magnetic disks, tapes) Capacity Number of words Number of bytes Unit of Transfer

More information

Cache Policies. Philipp Koehn. 6 April 2018

Cache Policies. Philipp Koehn. 6 April 2018 Cache Policies Philipp Koehn 6 April 2018 Memory Tradeoff 1 Fastest memory is on same chip as CPU... but it is not very big (say, 32 KB in L1 cache) Slowest memory is DRAM on different chips... but can

More information

Computer Architecture and Engineering. CS152 Quiz #2. March 3rd, Professor Krste Asanovic. Name:

Computer Architecture and Engineering. CS152 Quiz #2. March 3rd, Professor Krste Asanovic. Name: Computer Architecture and Engineering CS152 Quiz #2 March 3rd, 2009 Professor Krste Asanovic Name: Notes: This is a closed book, closed notes exam. 80 Minutes 10 Pages Not all questions are of equal difficulty,

More information

CSE COMPUTER USE: Fundamentals Test 1 Version D

CSE COMPUTER USE: Fundamentals Test 1 Version D Name:, (Last name) (First name) Student ID#: Registered Section: Instructor: Lew Lowther Solutions York University Faculty of Pure and Applied Science Department of Computer Science CSE 1520.03 COMPUTER

More information

CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.

CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng. CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng. Part 4: Memory Organization Our goal: understand the basic types of memory in computer understand memory hierarchy and the general process to access memory

More information

ECE 485/585 Midterm Exam

ECE 485/585 Midterm Exam ECE 485/585 Midterm Exam Time allowed: 100 minutes Total Points: 65 Points Scored: Name: Problem No. 1 (12 points) For each of the following statements, indicate whether the statement is TRUE or FALSE:

More information

William Stallings Computer Organization and Architecture 10 th Edition Pearson Education, Inc., Hoboken, NJ. All rights reserved.

William Stallings Computer Organization and Architecture 10 th Edition Pearson Education, Inc., Hoboken, NJ. All rights reserved. + William Stallings Computer Organization and Architecture 10 th Edition 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. 2 + Chapter 4 Cache Memory 3 Location Internal (e.g. processor registers,

More information

IEC MMS Client Driver Help Kepware Technologies

IEC MMS Client Driver Help Kepware Technologies IEC 61850 MMS Client Driver Help 2013 Kepware Technologies 2 Table of Contents Table of Contents 2 Help 3 Overview 3 Device Setup 4 Automatic Configuration 4 Connection 5 Communication 8 Control 9 Tag

More information

28 Simply Confirming On-site Status

28 Simply Confirming On-site Status 28 Simply Confirming On-site Status 28.1 This chapter describes available monitoring tools....28-2 28.2 Monitoring Operational Status...28-5 28.3 Monitoring Device Values... 28-11 28.4 Monitoring Symbol

More information

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.

More information

CAM Content Addressable Memory. For TAG look-up in a Fully-Associative Cache

CAM Content Addressable Memory. For TAG look-up in a Fully-Associative Cache CAM Content Addressable Memory For TAG look-up in a Fully-Associative Cache 1 Tagin Fully Associative Cache Tag0 Data0 Tag1 Data1 Tag15 Data15 1 Tagin CAM Data RAM Tag0 Data0 Tag1 Data1 Tag15 Data15 Tag

More information

Memory Management Prof. James L. Frankel Harvard University

Memory Management Prof. James L. Frankel Harvard University Memory Management Prof. James L. Frankel Harvard University Version of 5:42 PM 25-Feb-2017 Copyright 2017, 2015 James L. Frankel. All rights reserved. Memory Management Ideal memory Large Fast Non-volatile

More information

<Insert Picture Here> End-to-end Data Integrity for NFS

<Insert Picture Here> End-to-end Data Integrity for NFS End-to-end Data Integrity for NFS Chuck Lever Consulting Member of Technical Staff Today s Discussion What is end-to-end data integrity? T10 PI overview Adapting

More information

Unit 2: Data Storage CS 101, Fall 2018

Unit 2: Data Storage CS 101, Fall 2018 Unit 2: Data Storage CS 101, Fall 2018 Learning Objectives After completing this unit, you should be able to: Evaluate digital circuits that use AND, OR, XOR, and NOT. Convert binary integers to/from decimal,

More information

EEC 483 Computer Organization

EEC 483 Computer Organization EEC 48 Computer Organization 5. The Basics of Cache Chansu Yu Caches: The Basic Idea A smaller set of storage locations storing a subset of information from a larger set (memory) Unlike registers or memory,

More information

registers data 1 registers MEMORY ADDRESS on-chip cache off-chip cache main memory: real address space part of virtual addr. sp.

registers data 1 registers MEMORY ADDRESS on-chip cache off-chip cache main memory: real address space part of virtual addr. sp. 13 1 CMPE110 Computer Architecture, Winter 2009 Andrea Di Blas 110 Winter 2009 CMPE Cache Direct-mapped cache Reads and writes Cache associativity Cache and performance Textbook Edition: 7.1 to 7.3 Third

More information

Memory Hierarchy Design (Appendix B and Chapter 2)

Memory Hierarchy Design (Appendix B and Chapter 2) CS359: Computer Architecture Memory Hierarchy Design (Appendix B and Chapter 2) Yanyan Shen Department of Computer Science and Engineering 1 Four Memory Hierarchy Questions Q1 (block placement): where

More information

Birkbeck (University of London) Department of Computer Science and Information Systems. Introduction to Computer Systems (BUCI008H4)

Birkbeck (University of London) Department of Computer Science and Information Systems. Introduction to Computer Systems (BUCI008H4) Birkbeck (University of London) Department of Computer Science and Information Systems Introduction to Computer Systems (BUCI008H4) CREDIT VALUE: none Spring 2017 Mock Examination SUMMARY ANSWERS Date:

More information

ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014

ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

6.004 Tutorial Problems L20 Virtual Memory

6.004 Tutorial Problems L20 Virtual Memory 6.004 Tutorial Problems L20 Virtual Memory Page Table (v + p) bits in virtual address (m + p) bits in physical address 2 v number of virtual pages 2 m number of physical pages 2 p bytes per physical page

More information

registers data 1 registers MEMORY ADDRESS on-chip cache off-chip cache main memory: real address space part of virtual addr. sp.

registers data 1 registers MEMORY ADDRESS on-chip cache off-chip cache main memory: real address space part of virtual addr. sp. Cache associativity Cache and performance 12 1 CMPE110 Spring 2005 A. Di Blas 110 Spring 2005 CMPE Cache Direct-mapped cache Reads and writes Textbook Edition: 7.1 to 7.3 Second Third Edition: 7.1 to 7.3

More information

Solution : mov R0, mov R3,0 mov R4,31 movu R2,0x0001 mov R5,0 andu R1,R0,0xffff

Solution : mov R0, mov R3,0 mov R4,31 movu R2,0x0001 mov R5,0 andu R1,R0,0xffff Q4. Write an ARM assembly program that checks if a 32-bit number is a palindrome. Assume that the input is available in r 3. The program should set r 4 to 1 if it is a palindrome, otherwise r 4 should

More information

ECE 485/585 Midterm Exam

ECE 485/585 Midterm Exam ECE 485/585 Midterm Exam Time allowed: 100 minutes Total Points: 65 Points Scored: Name: Problem No. 1 (12 points) For each of the following statements, indicate whether the statement is TRUE or FALSE:

More information

ארכיטקטורת יחידת עיבוד מרכזי ת

ארכיטקטורת יחידת עיבוד מרכזי ת ארכיטקטורת יחידת עיבוד מרכזי ת (36113741) תשס"ג סמסטר א' July 2, 2008 Hugo Guterman (hugo@ee.bgu.ac.il) Arch. CPU L8 Cache Intr. 1/77 Memory Hierarchy Arch. CPU L8 Cache Intr. 2/77 Why hierarchy works

More information

Physical characteristics (such as packaging, volatility, and erasability Organization.

Physical characteristics (such as packaging, volatility, and erasability Organization. CS 320 Ch 4 Cache Memory 1. The author list 8 classifications for memory systems; Location Capacity Unit of transfer Access method (there are four:sequential, Direct, Random, and Associative) Performance

More information

CSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Recall

CSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Recall CSCI 402: Computer Architectures Memory Hierarchy (2) Fengguang Song Department of Computer & Information Science IUPUI Recall What is memory hierarchy? Where each level is located? Each level s speed,

More information

Chapter 7: Large and Fast: Exploiting Memory Hierarchy

Chapter 7: Large and Fast: Exploiting Memory Hierarchy Chapter 7: Large and Fast: Exploiting Memory Hierarchy Basic Memory Requirements Users/Programmers Demand: Large computer memory ery Fast access memory Technology Limitations Large Computer memory relatively

More information

LECTURE 11. Memory Hierarchy

LECTURE 11. Memory Hierarchy LECTURE 11 Memory Hierarchy MEMORY HIERARCHY When it comes to memory, there are two universally desirable properties: Large Size: ideally, we want to never have to worry about running out of memory. Speed

More information

User/Phone Add Configuration

User/Phone Add Configuration CHAPTER 91 The following topics contain information on adding and configuring end users at the End User, Phone, DN, and LA Configuration window: User and Device Configuration Settings, page 91-1 Adding

More information

Read this before starting!

Read this before starting! Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,

More information

University of Nevada, Reno. CacheVisual: A Visualization Tool for Cache Simulation

University of Nevada, Reno. CacheVisual: A Visualization Tool for Cache Simulation University of Nevada, Reno CacheVisual: A Visualization Tool for Cache Simulation A professional paper submitted in partial fulfillment of the requirements for the degree of Masters of Science in Computer

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young Department of Computer Sciences University of Texas at Austin Last updated: August 26, 2014 at 08:54 CS429 Slideset 20: 1 Cache

More information

Decimal/Binary Conversion on the Soroban

Decimal/Binary Conversion on the Soroban Decimal/Binary Conversion on the Soroban Conversion of a whole number from decimal to binary This method uses successive divisions by two, in place, utilizing a simple right-to-left algorithm. The division

More information

CSE141 Problem Set #4 Solutions

CSE141 Problem Set #4 Solutions CSE141 Problem Set #4 Solutions March 5, 2002 1 Simple Caches For this first problem, we have a 32 Byte cache with a line length of 8 bytes. This means that we have a total of 4 cache blocks (cache lines)

More information

Programming Assignment 3

Programming Assignment 3 UNIVERSITY OF NEBRASKA AT OMAHA Computer Science 4500/8506 Operating Systems Summer 2017 Programming Assignment 3 Introduction For this programming assignment you are to write a C, C++, Java, or Python

More information

Cache Memory Mapping Techniques. Continue to read pp

Cache Memory Mapping Techniques. Continue to read pp Cache Memory Mapping Techniques Continue to read pp. 289-305 Cache Memory Mapping Again cache memory is a small and fast memory between CPU and main memory A block of words have to be brought in and out

More information

ECE7995 Caching and Prefetching Techniques in Computer Systems. Lecture 8: Buffer Cache in Main Memory (I)

ECE7995 Caching and Prefetching Techniques in Computer Systems. Lecture 8: Buffer Cache in Main Memory (I) ECE7995 Caching and Prefetching Techniques in Computer Systems Lecture 8: Buffer Cache in Main Memory (I) 1 Review: The Memory Hierarchy Take advantage of the principle of locality to present the user

More information

3) Cache, money. Dollar bills, y all. (24 min, 15 pts)

3) Cache, money. Dollar bills, y all. (24 min, 15 pts) Login: cs61c- Answers 3) Cache, money. Dollar bills, y all. (24 min, 15 pts) Suppose we have a standard 32-bit byte-addressed MIPS machine, a single direct-mapped 32KiB cache, a write-through policy, and

More information

COSC 3406: COMPUTER ORGANIZATION

COSC 3406: COMPUTER ORGANIZATION COSC 3406: COMPUTER ORGANIZATION Home-Work 5 Due Date: Friday, December 8 by 2.00 pm Instructions for submitting: Type your answers and send it by email or take a printout or handwritten (legible) on paper,

More information

MCS-284 Final Exam Serial #:

MCS-284 Final Exam Serial #: MCS-284 Final Exam Serial #: This exam is closed-book and mostly closed-notes. You may, however, use a single 8 1/2 by 11 sheet of paper with hand-written notes for reference. (Both sides of the sheet

More information

Contents. Main Memory Memory access time Memory cycle time. Types of Memory Unit RAM ROM

Contents. Main Memory Memory access time Memory cycle time. Types of Memory Unit RAM ROM Memory Organization Contents Main Memory Memory access time Memory cycle time Types of Memory Unit RAM ROM Memory System Virtual Memory Cache Memory - Associative mapping Direct mapping Set-associative

More information

OP Handheld Manual. BALOGH 7699 Kensington Court Brighton, MI (248)

OP Handheld Manual. BALOGH 7699 Kensington Court Brighton, MI (248) OP Handheld Manual BALOGH 7699 Kensington Court Brighton, MI 48116-8561 (248) 486-7343 Notes are used to call attention to information that is significant to the understanding and operation of equipment.

More information

Cache Memory. Content

Cache Memory. Content Cache Memory Raul Queiroz Feitosa Content Memory Hierarchy Principle of Locality Some Definitions Cache Architectures Fully Associative Direct Mapping Set Associative Replacement Policy Main Memory Update

More information

Name: CMSC 313 Fall 2001 Computer Organization & Assembly Language Programming Exam 1. Question Points I. /34 II. /30 III.

Name: CMSC 313 Fall 2001 Computer Organization & Assembly Language Programming Exam 1. Question Points I. /34 II. /30 III. CMSC 313 Fall 2001 Computer Organization & Assembly Language Programming Exam 1 Name: Question Points I. /34 II. /30 III. /36 TOTAL: /100 Instructions: 1. This is a closed-book, closed-notes exam. 2. You

More information

Introduction to Computer Science Midterm 3 Fall, Points

Introduction to Computer Science Midterm 3 Fall, Points Introduction to Computer Science Fall, 2001 100 Points Notes 1. Tear off this sheet and use it to keep your answers covered at all times. 2. Turn the exam over and write your name next to the staple. Do

More information

Read this before starting!

Read this before starting! Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Fall Semester,

More information

and denominators of two fractions. For example, you could use

and denominators of two fractions. For example, you could use Learning Goal denominators. Open Question and denominators of two fractions. For example, you could use and 0. Make sure that some of your fractions are improper and some are proper. Make sure that some

More information

Computer Organization. Chapter 12: Memory organization

Computer Organization. Chapter 12: Memory organization Computer Organization Chapter 12: Memory organization Memory Organization Recall: Information is stored in the memory as a collection of bits. Collection of bits that are stored or retrieved simultaneously

More information

ΗΥ345 Operating Systems. Recitation 2 Memory Management - Solutions -

ΗΥ345 Operating Systems. Recitation 2 Memory Management - Solutions - ΗΥ345 Operating Systems Recitation 2 Memory Management - Solutions - Problem 7 Consider the following C program: int X[N]; int step = M; //M is some predefined constant for (int i = 0; i < N; i += step)

More information

Spanning Tree Configuration

Spanning Tree Configuration Using the Console Interface Spanning Tree Configuration The Spanning Tree Configuration Menu screen (Figure 3-29) allows you to view spanning tree parameters and configure individual switch ports to participate

More information

UNIT:4 MEMORY ORGANIZATION

UNIT:4 MEMORY ORGANIZATION 1 UNIT:4 MEMORY ORGANIZATION TOPICS TO BE COVERED. 4.1 Memory Hierarchy 4.2 Memory Classification 4.3 RAM,ROM,PROM,EPROM 4.4 Main Memory 4.5Auxiliary Memory 4.6 Associative Memory 4.7 Cache Memory 4.8

More information

V. Primary & Secondary Memory!

V. Primary & Secondary Memory! V. Primary & Secondary Memory! Computer Architecture and Operating Systems & Operating Systems: 725G84 Ahmed Rezine 1 Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM)

More information

Binghamton University. CS-220 Spring Cached Memory. Computer Systems Chapter

Binghamton University. CS-220 Spring Cached Memory. Computer Systems Chapter Cached Memory Computer Systems Chapter 6.2-6.5 Cost Speed The Memory Hierarchy Capacity The Cache Concept CPU Registers Addresses Data Memory ALU Instructions The Cache Concept Memory CPU Registers Addresses

More information

CS 31: Intro to Systems Caching. Kevin Webb Swarthmore College March 24, 2015

CS 31: Intro to Systems Caching. Kevin Webb Swarthmore College March 24, 2015 CS 3: Intro to Systems Caching Kevin Webb Swarthmore College March 24, 205 Reading Quiz Abstraction Goal Reality: There is no one type of memory to rule them all! Abstraction: hide the complex/undesirable

More information

Caches. Hiding Memory Access Times

Caches. Hiding Memory Access Times Caches Hiding Memory Access Times PC Instruction Memory 4 M U X Registers Sign Ext M U X Sh L 2 Data Memory M U X C O N T R O L ALU CTL INSTRUCTION FETCH INSTR DECODE REG FETCH EXECUTE/ ADDRESS CALC MEMORY

More information

Q1: Finite State Machine (8 points)

Q1: Finite State Machine (8 points) Q1: Finite State Machine (8 points) Answer the questions below for the finite state machine in this diagram: 1. Complete the truth table shown below. (2 points) Input Output State In State Out S 0 = 00

More information

NAME: 1a. (10 pts.) Describe the characteristics of numbers for which this floating-point data type is well-suited. Give an example.

NAME: 1a. (10 pts.) Describe the characteristics of numbers for which this floating-point data type is well-suited. Give an example. MSU CSC 285 Spring, 2007 Exam 2 (5 pgs.) NAME: 1. Suppose that a eight-bit floating-point data type is defined with the eight bits divided into fields as follows, where the bits are numbered with zero

More information

Perform page replacement. (Fig 8.8 [Stal05])

Perform page replacement. (Fig 8.8 [Stal05]) Virtual memory Operations and policies Chapters 3.4. 3.7 1 Policies and methods Fetch policy (Noutopolitiikka) When to load page to memory? Placement policy (Sijoituspolitiikka ) Where to place the new

More information

Question 6: Cache in While You Can (17 points, 26 Minutes)

Question 6: Cache in While You Can (17 points, 26 Minutes) Question 6: Cache in While You Can (17 points, 26 Minutes) Consider a single 4KiB cache with 512B blocks and a write back policy. Assume a 32 bit address space. a) If the cache were direct mapped, # of

More information

Memory. Objectives. Introduction. 6.2 Types of Memory

Memory. Objectives. Introduction. 6.2 Types of Memory Memory Objectives Master the concepts of hierarchical memory organization. Understand how each level of memory contributes to system performance, and how the performance is measured. Master the concepts

More information

Table 12.2 Information Elements of a File Directory

Table 12.2 Information Elements of a File Directory Table 12.2 Information Elements of a File Directory Basic Information File Name File Type File Organization Name as chosen by creator (user or program). Must be unique within a specific directory. For

More information

Last class. Caches. Direct mapped

Last class. Caches. Direct mapped Memory Hierarchy II Last class Caches Direct mapped E=1 (One cache line per set) Each main memory address can be placed in exactly one place in the cache Conflict misses if two addresses map to same place

More information