Circuits. L3: Fabrication and Layout -1 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Transcription

1 EE60: CMOS Analog Circuits L: Fabrication and Layout - (8.8.0) B. Mazhari Dept. of EE, IIT Kanpur

2 Suppose we have a Silicon wafer which is P-type and we wish to create a region within it which is N-type as shown below: N + P-Silicon This can be done by carrying out diffusion/implantation of N-type dopant in the structure shown below. SiO The SiO acts a as a barrier P-Silicon and prevents diffusion of dopants through it. As a result the N-type region is created only in the region where Silicon is exposed

3 A window in SiO can be created by first covering the whole Silicon surface with oxide through the oxidation process. Next the Silicon surface is coated with an organic material which is sensitive to light called Photoresist. A positive photoresist undergoes changes upon exposure which makes it easier to dissolve in a developer solution We next need a Mask which specifies the location and dimension of N- region. It is basically a glass plate which has opaque and transparent regions. Wherever we want the photoresist to remain, that region is opaque and wherever we wish to remove the photoresist that region is made transparent. Light Mask P-Silicon The mask is placed either in contact or in close proximity to the resist coated Silicon wafer and exposed to light as illustrated below

4 After this step of Photolithography, the exposed photoresist is removed using a developer solution and we obtain the following structure: Photoresist P-Silicon SiO Next the whole wafer is dipped in HF acid to Etch the exposed oxide to obtain the following structure: Photoresist P-Silicon SiO SiO Next the photoresist is removed to obtain the structure required for carrying out diffusion. P-Silicon

5 Fabrication: simplified view SiO SiO Poly Poly P + N + N + N + P + P + N-well P-Silicon P-Silicon Transfer of pattern from mask to photoresist ----photolithography Transfer of pattern from photoresist to silicon Various processing steps.

6 S D D S B Active area Active area 6

7 The fabrication process begins with a Silicon substrate P-epilayer N A ~0 cm - Substrate thickness ~ 77µm for a 00mm wafer size Substrate - P-type 7

8 . AP-type Transistor requires creation of an N-well well. N-Well N-Well. Active areas are defined: Active Mask N-Well A A N A A 8

9 . Poly-Silicon Gate Definition Poly Mask N-Well. N diffusion - P-Select Mask N-Well 9

10 . P diffusion - N-Select Mask N-Well 6. Contacts : Contact cut Mask N-Well 0

11 7. Metal - Mask N-Well 8. Via Mask 9. Metal - Mask

12 Multi layers of Metal

13 Physicaly Design requires generation of geometrical Drawings for each one of the masks Design Rules are constraints that the design must obey in order to guarantee that the circuit can be fabricated without errors and with reasonable yield. These rules come about through interaction of electrical and reliability constraints with the capabilities of the fabrication technology.

14 Design Rules Design rules are specified as a set of layers and rules for patterns within layers (intra layer) and between objects on different layers. Some basic rules for a scalable SCMOS process are given below in terms of the parameter The minimum feature size is λ, so that if a technology is specified as m process, it implies thatt λ= 0. m.

15 Design Rules Same Potential Different Potential 9 0 Well or Polysilicon 6 0 Active Metal Contact or Via Hole Select

16 Design Rules o r s t n i a Tr rr ar r 6

17 Design Rules Via Metal to Metal to Poly Contact Active Contact 7

18 Design Rules Select Substrate Well 8

19 Example : spacing between diffusion wires has to be larger than a certain minimum value. Fabrication process is not perfect. -imperfections in Masking step, resist removal, oxide etching and diffusion cause the wire dimensions to from what they are specified on the mask. P-type 9

20 Design Rules : Origin N + N + P 0

21 CMOS Inverter/Amplifier : Layout V DD V DD V Bias V IN V OUT V OUT V IN GND GND CS amplifier with active PMOS Load relative placement and orientation of the transistors choice of interconnect and routing

22 CMOS Inverter : Layout. Make the NMOS D S. Make the contact between ground and source of NMOS GND

23 . Make the substrate contact for the NMOS GND

24 . The drain of NMOS has to be connected to drain of PMOS. SO we need a metal contact to the drain GND

25 . Next the PMOS transistor has to be drawn. The PMOS is fabricated in an N-well. The design rules dictate that the well boundary be away from all active regions by at least N-well Edge GND

26 6. P-type Tr. With Contacts VDD VDD 6 N-well Edge GND 6

27 7. Substrate contact is added VDD VDD 6 N-well Edge GND 7

28 8. Gates are connected VDD VDD 6 N-well Edge V IN V OUT V IN VOUT GND 8

29 Layout Analysis Area : x = 67. VDD Aspect ratio = Height / Width / NMOS: Drain Area = 9 ; Perimeter = PMOS: Drain Area = 0 ; V IN Perimeter = 6 6 N-well Edge V OUT poly area over field oxide ~ 80. Metal- area and perimeter at the output ~60, 6 GND 9

30 Capacitances : 0. µm technology VDD C OX (ff/ m ) C poly (ff/ m ) C M (ff/ m ) C 6 M (ff/ m) N-well Edge V IN V OUT -poly capacitance ~0.6fF -metal- capacitance ~0.fF (fringe component is x ) GND 0

31 Inverter : Net capacitance VDD VDD 6 6 C T N-well Edge N-well Edge C ( C C ) T gsn gdn V IN V V IN OUT V OUT ( C C ) gsp gdp ( C C ) dbn dbp GND GND C poly C metal C T ~.ff; ff; ffdue.ff to parasitic poly & M- capacitances delay about 9% higher with parasitic capacitances

32 Effect of Wire 00 m m The capacitance due to the metal interconnect is.ff, 7% of which is due to the fringe component. The wire capacitance is x.76 as large as the gate capacitance of inverter-! The wire capacitance is 7. x as large as the gate capacitance of inverter-! for 0.8µm technology Wire capacitance is the most significant capacitance sub-micron technologies. for deep

33 Identify the layout VDD GND GND M M V DD

34 Why multiple contacts to the source?

35 Design Rules : Design Reuse -rules are a simplified representation that have some advantages as well as disadvantages. Rules are easy to understand and remember making the design easier and less prone to error. Use of rules gives a design representation which is independent of technology.

36 Design reuse : Technology independent representation Technology is changing rapidly and circuit complexity is continuously increasing One of the ways of coping with this increased circuit complexity in an almost fixed design time is to employ the technique of Design Reuse A technology independent representation which can be easily technology-mapped or made technology specific facilitates design reuse. 6

37 Design reuse : Technology independent representation Specs. Specs. Design at higher abstraction level Tech. Info Design Design Intermediate Design (Tech. Ind.) Tech. Info Tech. Mapping Final Design 7

38 Design reuse : Technology independent representation Although rules make tech. mapping easy, they result in inferior design rules represent worst-case rules Technology Min. Min. Min. Feature size Feature size Feature size L L L m m 0 m m 0. m 0. m m m 8

39 Technology Min. Feature Min. Feature Min. Feature size L size L size L m m 0 m m 0. m 0. m m m Technology Min. Feature size L Min. Feature size L Min. Feature size L m 0. m m 0. m 8 9

40 Design reuse : Technology independent representation Technology Min. Feature Min. Feature Min. Feature size L size L size L m 0. m m 0. m 8 Common Design Rules : L : L : 0 L : 8 Rules very conservative Benefits of scaling to some extent lost 0

41 Need a better representation that can take full advantage of design rules Since rules pertain to actual widths, separations etc, the new representation would need to have no size or dimensional information. In other words, the layout representation would be a symbolic layout which includes all design information except for the dimensions. Stick Layout

42 Stick Layout VDD V DD X N-well Edge 6 i/p X X O/P X V IN V OUT X GND GND

43 Stick Layout: CMOS Inverter V DD X V DD V IN V OUT i/p X X X O/P GND X GND X V DD X X i/p X O/P X X X GND