Behavioral modeling of crosswafer chip-to-chip process induced non-uniformity. W. CLARK COVENTOR, Villebon sur Yvette, France

Transcription

1 Behavioral modeling of crosswafer chip-to-chip process induced non-uniformity W. CLARK COVENTOR, Villebon sur Yvette, France

2 Variability Concerns Variability is a major concern of any semiconductor process Variability imposes limits (guard-bands) on performance, density, power Variability is not scaling as fast as feature size Increasing process complexity drives increased variability Multiple lithography steps - LE n Sub-lithography feature processing - SADP, SAQP, Understanding and controlling the across wafer systematic variations are key to feed forward process control Process simulation provides a methodology to predict and compensate for this systematic variation

3 Future Technology Trends Complex Devices: Vertical III-V NanoWire Complex Patterning: SADP SAQP SAOP? Complex Structures: BEOL Passives & Memory All the future technology trends point to increased structural complexity Cost and development cycle-time will increase Systematic structural defectivity becomes the limiter to yield-ramp The role of Process Integration becomes essential to development success Process Integrators need to be armed with the right tools Traditional TCAD modeling is useful for individual transistors Ab-Initio modeling is useful for novel materials and unit processes But the process integrator typically relies on running experimental wafers! Trial-and-Error Silicon Engineering is NOT ACCEPTABLE!!!

4 What is SEMulator3D? A Powerful 3D Semiconductor Virtual Fabrication Platform Layout Editor: Design, OPC, PrintSim, etc. Process Editor: Step-by-Step Process Behavioral Description 3D Viewer: RMG FinFET Demo Self-Aligned Contact TFMHM BEOL w/ SAV Applicable to ANY process & ANY layout Replaces build & test with accurate 3D modeling of large areas & complex process sequences Provides validation and visualization of relationships between design and process Provides a predictive view of design-technology interactions

5 SEMulator3D 5.0 Automation Package Provides batch processing and automated 3D structure searches, with metrology data and numerical output Wafer mask Wafer mask Contains the following three components Automation AFM Virtual Metrology In-line measurements Structure Search Mark violations of 3D geometric criteria Line-to-Line CD Sidewall Angle Step Film Thickness Expeditor Batch mode for DOE or variation studies

6 SEMulator3D 5.0 Automation Virtual Metrology Provide automatic measurements on critical technology parameters Mimic real in-fab metrology, replace slow out-of-fab destructive characterization Beyond in-line metrology such as measurements on layers underneath others Specify Measurement Regions Measure Top CD Measure SWA Measure Spacing Measure Film Thickness Virtual Metrology Measurement Options Get Numerical Metrology Results

7 SEMulator3D 5.0 Automation Expeditor Batch processing tool Automated, spreadsheet-driven massively parallel parameter studies Works with Virtual Metrology to create numerical DOE outputs Generate 3D models for each run Input Run Parameters Example: DOE Study on FinFET Epitaxy, with <100> notched wafer Dependence on pre-epitaxy fin erosion and epitaxial conditions

8 Cross-Wafer Uniformity Unit process cross-wafer behavior is easily validated from inline metrology Input Full Wafer Maps The cross-wafer requirement is integrated and electrical Costly & time-consuming to verify on HW Typical practice involves individual process optimization, driving toward a flat profile for all processes SEMulator3D provides a predictive methodology for evaluating integrated structural results (using virtual metrology) due to multiple forms of variation across the wafer (using Expeditor) Process Co-optimization Intelligent APC Output Full Wafer Maps PR ARC OPL TiN Cap LowK BLoK M x Litho1 M x Litho2 V (x-1) SAV Etch Trench Etch Liner/CuBS CMP 8 Coventor, Inc. SEMICON EUROPA 7 Oct 2015

9 Visibility Process Concepts Line of sight processing For example - The 2D trench shown below sees only a fraction of the flux that a point on the surface would see Source distribution A measure of the dispersion of the source flux

10 Wafer TiltTwist Conventions Source Wafer normal Tilt Die Path length Twist

11 Process steps to form test structure Coventor, Inc. SEMICON EUROPA 7 Oct 2015

12 Wafer maps of tilt/twist magnitudes For visibility steps Coventor, Inc. SEMICON EUROPA 7 Oct 2015

13 Build cross sections in focal center and edge Focal center Focal edge Note west to east offset in Fin CD due to visibility processing

14 Wafer Map of West/East and North/South fin delta The magnitude of the offset is proportional to the size of the dot while the polarity is indicated by the color scale Note that due to the tool/process assumptions made, the center of focus of the three visibility steps were not identical. So the final build response will be a process dependent average of the visibility processes. This feature has not been readily available before on an integrated process simulation

15 Summary/Conclusion Demonstrated a behavioral model approach to comprehending the systematic variation across wafer induced by visibility processes Demonstrated the efficacy of virtual fabrication Demonstrated processing average effect of multiple independent processes on the final response This experiment ~150 chip sites ran in less than 9 hours Thank you for your attention

16 Build Animation Coventor, Inc. SEMICON EUROPA 7 Oct 2015

17 Build animation Coventor, Inc. SEMICON EUROPA 7 Oct 2015

18 Build animation Coventor, Inc. SEMICON EUROPA 7 Oct 2015