Workshop on Digital Circuit Design in FPGA


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1 Workshop on Digital Circuit Design in FPGA Session1 Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Website: kader05cuet.wordpress.com
2 The fieldprogrammable gate array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field hence the name "fieldprogrammable". You can use an FPGA to implement any logical function that an applicationspecific integrated circuit (ASIC) or, applicationspecific standard product (ASSP) could perform, but the ability to update the functionality after shipping offers advantages for many applications. What is an FPGA?
3 FPGA Architecture IOB Input/Output Block. CLB Configurable Logic Block. PSM Programmable Switch Matrix. Connection Lines Clock Circuitry 3
4 FPGA Vs Microcontroller Microcontroller: Microcomputer in a single chip. Configuring a predefined hardware by programming. FPGA: Developing Hardware by programming 4
5 FPGA Programming FPGA Programming Schematic Entry Hardware Description language Verilog HDL VHDL RTL Verilog Code Structural Verilog Code Behavioral Verilog Code 5
6 Schematic Design in FPGA Implementation of Full adder circuit X Y S = X Y Z Z C = Z(X Y) + XY Steps: a) Open a new project Wizard. b) Open a new schematic file. c) Draw the circuit. d) Compilation. e) Pin Planer. f) Compilation g) Upload 6
7 Open a new project Wizard. Schematic Design in FPGA(Cont.)
8 Family and Device Settings Schematic Design in FPGA(Cont.) 8
9 Drawing circuit in New Schematic File Schematic Design in FPGA(Cont.)
10 Pin Planner Schematic Design in FPGA(Cont.)
11 Loading Program Schematic Design in FPGA(Cont.) 11
12 Verilog HDL Structural Verilog Code
13 Verilog HDL Structural Verilog Code
14 Verilog HDL RTL Verilog Code RTL Verilog Coding of Digital Circuit Structural Verilog code is not practicable for designing complex circuit. In that case, RTL Verilog code is used to design digital circuit. RTL Verilog code of a digital design can be written in two ways: 1) Using continuous assignment structures. 2) Using Procedural assignment structures. Continuous assignment Vs Procedural assignment It is named as continuous assignment because the assignments written in this procedure are evaluated continuously whereas in procedural assignment structure execution of a statement waits for the clock or other parameter. The expression (in continuous assignment structure) is evaluated whenever any of the operands changes. RTL coding using continuous assignment is usually used to model combinational circuit which is more complex than can be handled by structural modeling. The declaration module, input, output and endmodule are same as they are used in structural Verilog code. The difference is the keyword assign is used to write the continuous assignment. 14
15 RTL Verilog Code using Continuous Assignment RTL Verilog code using Continuous Assignment to follow the logic equations given below. Verilog Code: 15
16 RTL Verilog Code using Continuous Assignment BCD to Seven Segment Decoder by RTL Verilog Coding using Continuous assignment A BCD to sevensegment decoder is a combinational circuit that accepts a decimal digit in BCD and generates the appropriate outputs for the selection of segments in a display indicator used for displaying the decimal digit. The seven output of the decoder (a,b,c,d,e,f,g) select the corresponding segments in the display as shown in figure a. The numeric designation chosen to represent the decimal digit is shown in figure b. Design the BCD to seven segment decoder circuit. a: Segment designation b: Numerical designation for display 16
17 RTL Verilog Code using Continuous Assignment (Cont.) From truth table we obtaineda= (0,2,3,5,6,7,8,9) b= (0,1,2,3,4,7,8,9) c= (0,1,3,4,5,6,7,8,9) d= (0,2,3,5,6,8,9) e= (0,2,6,8) f= (0,4,5,6,8,9) g= (2,3,4,5,6,8,9) Don t care conditions, d= (10,11,12,13,14,15) 17
18 From truth table we obtaineda= (0,2,3,5,6,7,8,9) b= (0,1,2,3,4,7,8,9) c= (0,1,3,4,5,6,7,8,9) d= (0,2,3,5,6,8,9) e= (0,2,6,8) f= (0,4,5,6,8,9) g= (2,3,4,5,6,8,9) Don t care, d= (10,11,12,13,14,15) CD AB CD AB CD CD AB AB RTL Verilog Code using Continuous Assignment (Cont.) X X X X X X X X X X X X X X X X X X X X X X X X AB a= A+C+B D +BD CD AB b= B +C D +CD c= B +C +D d= A +B D +B C+BC D+CD CD CD AB 18 X X X X X X X X X X X X X X X X X X e= B D +CD f= A+C D +BD +BC g= A+B C+BC +BD
19 RTL Verilog Code using Continuous Assignment (Cont.) Logic Equations a= A+C+B D +BD b= B +C D +CD c= B +C +D d= A +B D +B C+BC D+CD e= B D +CD f= A+C D +BD +BC g= A+B C+BC +BD Verilog Code module seven_segment (a,b,c,d,e,f,g,a,b,c,d); input A,B,C,D; output a,b,c,d,e,f,g; assign a=a C (~B&~D) (B&D); assign b=(~b (~C&~D) (C&D)); assign c=b ~C D; assign d=a (~B&~D) (~B&C) (B&~C&D) (C&~D); assign e=(~b&~d) (C&~D); assign f=a (~C&~D) (B&~D) (B&~C); assign g=a (~B&C) (B&~C) (B&~D); endmodule 19
20 RTL Verilog Code using Continuous Assignment (Cont.) Verilog code to design 4bit addersubtractor circuit using continuous assignment structure. Verilog Code: 20
Workshop on Digital Circuit Design in FPGA
Organized by: Dept. of EEE Workshop on Digital Circuit Design in FPGA Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com
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