Keck-Voon LING School of Electrical and Electronic Engineering Nanyang Technological University (NTU), Singapore

Transcription

1 MPC on a Chip Keck-Voon LING (ekvling@ntu.edu.sg) School of Electrical and Electronic Engineering Nanyang Technological University (NTU), Singapore EPSRC Project Kick-off Meeting, Imperial College, London, 16 Oct 2009

2 Outline MPC on a Chip Toolbox a rapid prototyping tool QP solvers (Interior point and active set methods) on a FPGA reduced precision (16 bit mantissa) still works interior point vs active set methods Multiplexed MPC a strategy to reduce online computation ideally suited for FPGA implementation, potential for pipelining solving Ax=b problems the Multiplexed MPC way control-theoretic framework to analyse/design iterative solutions of Ax=b design and implementation of reduced precision Ax=b solvers

3 MPC on a Chip Toolbox To promote the MPC technology for embedded control Create a MPC Toolbox take an MPC problem from design to embedded implementation, especially on FPGA leading to a wider application of the embedded MPC technology options for embedded MPC Processor / DSP Programmable h/w / ASIC embedded => application specific

4 Prototyping Environment Matlab/Handel-C Algorithms are first developed in Matlab Translated the verified Matlab code into Handel-C (FPGA implementation) or C (microblaze) Compile Handel-C / C into bit file and download it to FPGA / Microblaze Matlab/Handel-C Cosimulation or Matlab/microblaze Cosimulation ω MPC implemented in MATLAB MPC implemented in FPGA MPC implemented in Microblaze 2) MPC calculations is performed on FPGA Plant Simulation 1) During every iteration, PC passes MPC parameters down to FPGA via UART 3) FPGA sends results back to PC via UART 4) 2 variants of MPC implementation on FPGA; 1 using Handel-C, the other using Microblaze processor Fig. 2 Prototyping of MPC on a Chip y

5 A Simple Test Script

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17 Swing-up and Balancing of an Inverted Pendulum RC10 board

18 FPGA Implementation Implemented on Celoxica RC203 prototyping board with a Xilinx XC2V3000 FPGA, coded with Handel-C. IEEE Single Precision Floating Point is used for both ASM and IPM Block RAMs are used for storage of QP problem matrices and intermediate calculation results Sequential implementation of both ASM and IPM ASM used more storage than IPM as a larger linear system is needed to be formed and solved Resources IPM ASM Clock rate 25 MHz 25 MHz LUTs 8,755 (30%) 8,773 (30%) FFs 2,153 ( 7%) 3,540 (12%) Block RAMs 22 (22%) 59 (61%)

19 Comparison of IPM on Various Embedded Platforms IPM performance measured on various embedded platforms On microcontrollers like STM32, soft core microprocessor like Microblaze, TI DSPs, Pentium processors and FPGAs Tested on 100 randomly generated QP problem of size nv=7, mc=71

20 Comparison of IPM on Various Embedded Platforms IPM performance measured on various embedded platforms On microcontrollers like STM32, soft core microprocessor like Microblaze, TI DSPs, Pentium processors and FPGAs Tested on 100 randomly generated QP problem of size nv=7, mc=71 All clock rates adjusted to 25MHz

21 IPM with Reduced Precision: Results Average number of iterations

22 IPM with Reduced Precision: Results Distribution of relative error For 23 bits mantissa QP solved with relative error, less than 1e-4: 38.8% less than 1e-2: 84.4% less than 1e-1: 97.4% QP unsolved: 0.5% For 20 bits mantissa QP solved with relative error, less than 1e-4: 28.2% less than 1e-2: 71.3% less than 1e-1: 94.4% QP unsolved: 0.63% For 16 bits mantissa QP solved with relative error, less than 1e-4: 16.8% less than 1e-2: 41.8% less than 1e-1: 80.1% QP unsolved: 1.88% For 12 bits mantissa QP solved with relative error, less than 1e-4: 1.66% less than 1e-2: 14.8% less than 1e-1: 44.6% Q unsolved: 12.0% Storage (in terms of word length of variables) could be reduced by up to 30%, and yet maintaining reasonably good QP solution.

23 IPM with Reduced Precision on MPC Application: Results Control Plots Using IPM (23 bits mantissa) Using IPM (20 bits mantissa) Using IPM (16 bits mantissa) Using IPM (12 bits mantissa)

24 IPM vs ASM: Convergence Speed (# of iterations) In general, for IPM, the number of iterations is around 11-14, not sensitive to the problem size. In contrast, for ASM, the number of iterations increases roughly linearly with the problem size. Number of iterations Number of iterations IPM Number of constraints, mc IPM Number of decision variables, nv Number of constraints, mc ASM ASM Number of decision variables, nv

25 IPM vs ASM, Complexity: Storage, # of Operations per Iteration The number of arithmetic operations for solving the linear system of equations is: For Gauss-Jordan elimination with pivoting,

26 IPM vs ASM, Complexity: No. of Operations Per Iteration For ASM, computation cost for solving the system of equations is dominating. However, for IPM, the fixed cost dominates. From the expressions in the table, for IPM, the ratio (time spent for solving Ax=b / total time to solve a QP problem) is lower than. This is confirmed by the following experiment results (right plot): ASM IPM

27 Overall Performance: Computation Time No. of iterations Solving system of linear equations Others dominating costs IPM Insensitive to Increase with Fixed cost; increase with ASM Increase linearly with Increase with No The overall performance can be quantified by the computation time required to obtain the solution of a QP problem. As seen from the above table, there are several factors that can affect the performances of ASM and IPM algorithms. Therefore, neither ASM nor IPM would always be superior to the other.

28 Overall Performance: Computation Time When is small, ASM outperforms IPM, since the number of iterations required by ASM is small. But, when is large, the number of iterations becomes large as well. In this case, IPM is more efficient. This suggests that, when the problem is large, IPM is preferred. Computational time (ms) Computational time (ms) Number of constraints, mc 50 IPM IPM Number of decision variables, nv ASM Number of constraints, mc ASM Number of decision variables, nv

29 Multiplexed MPC

30 Standard MPC - limitations Constrained Model Predictive Control (MPC) needs to solve constrained optimization problems on-line, whose computational complexity is m: number of control inputs N u : control horizon Embedded application has limited computational resources System with fast dynamics requires short computational time to find a solution

31 Basic idea of MMPC Synchronous MPC (SMPC) u 1 u 2 T Time Multiplexed MPC (MMPC) u 1 T u 2 T/2 Time

32 View as periodic SISO plant k+ 1 k j j, k j= 1 m x = Ax + B Δu x = Ax + + B Δ u k 1 k σ ( k) k where σ ( k) = ( k mod m) + 1 and Δ uk =Δu σ ( k), k

33 Features of MMPC Divide the original MPC problem into a sequence of optimization Solve each subsystem sequentially Reduced computational complexity scalable to many inputs Update subsystem controls as soon as the solution is available, all the inputs are updated sequentially Each control updated takes account of all the information available Periodic control

34 Computational steps in MPC Standard MPC set up Predictions: Y =Φ xk + GU T T T T QP :min U ( G G + λi) U 2 U G ( W Φxk ) subject to EU F At time step k 1. Measure xk T 2. Form G ( W Φxk ) 3. Solve QP U 4. Receding horizon, 5. Repeat step (1) u k

35 Multiplexed MPC Computational Steps T T T T MMPC re-group U into [ u0 u1... u m 1] and solve for u, u,..., sequentially at each time step k. 0 1 Thus, the MMPC predictions equation becomes Y =Φ x + gu + g u m 1 k 1 0 i= 1 i+ 1 i and the QP becomes min u ( g g I) u 2 u g ( W x g u ) T T T m λ Φ k i= 1 i+ 1 i subject to Eu 0 F smaller matrix, smaller QP, hence reduced on-line computational load in MMPC can start computing this term, and prepare for the next QP, as soon as u 0 is obtained.

36 MMPC on FPGA

37 Solving Mu=b iteratively -- MMPC way Let r = b Mu k r = b Mu MΔ u, since u = u +Δu k+ 1 k k k+ 1 k k+ 1 r = r MΔu k+ 1 k k k Solve Mu=b iteratively the MMPC way Plant model: r MMPC law: = r M Δu k+ 1 k σ( k) k Δ u = K r k σ( k) k Closed loop: r = ( I M K ) r k+ 1 σ( k) σ( k) k Stability can be ensured by design, σ(k+m)= σ(k)

38 Solving Mu=b iteratively -- MMPC way Jacobi s method: M = U+D+L, K = D^(-1), solve each subsystem simultaneously Gauss-Seidel: K = (D+L)^(-1), solve each subsystem sequentially, similar to MMPC Multiplexed MPC, a generalised scheme to solve Mu=b iteratively (?)

39 Mu = b in MPC/QP problems M changes in some known manner in the QP iterations Use robust control idea to solve Mu = b

40 Reduced precision Mu=b solver