DATA REUSE ANALYSIS FOR AUTOMATED SYNTHESIS OF CUSTOM INSTRUCTIONS IN SLIDING WINDOW APPLICATIONS
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1 Georgios Zacharopoulos Giovanni Ansaloni Laura Pozzi DATA REUSE ANALYSIS FOR AUTOMATED SYNTHESIS OF CUSTOM INSTRUCTIONS IN SLIDING WINDOW APPLICATIONS Università della Svizzera italiana (USI Lugano), Faculty of Informatics IMPACT 2017 Jan 23, 2017 Stockholm, Sweden
2 INTRODUCTION 2 MOORE S LAW - DENNARD SCALING Expectation Performance should keep increasing Reality Performance is NOT increasing anymore
3 INTRODUCTION BREAKDOWN OF DENNARD SCALING Single core > Multiple cores Dark Silicon 3
![INTRODUCTION 4 HETEROGENEOUS ERA Multiple cores > Heterogeneous Computing Need for Specialised HW [1] [1]](/docs-images/89/100586523/images/4-0.jpg "http://developer.amd.com/resources/heterogeneous-computing/what-is-heterogeneous-system-architecture-hsa/")
4 INTRODUCTION 4 HETEROGENEOUS ERA Multiple cores > Heterogeneous Computing Need for Specialised HW [1] [1]
5 BACKGROUND 5 SPECIALISATION AND PERFORMANCE ASICS CPU + HW ACCELERATORS SPECIALISATION GENERAL PURPOSE CPU DOMAIN SPECIFIC PROCESSORS (ADSPS) APPLICATION SPECIFIC INSTRUCTION-SET PROCESSORS (ASIPS) PERFORMANCE
6 RELATED WORK 6 DATA TRANSFER IS THE BOTTLENECK Accelerate data transfer between accelerators and [4] [5] memory Custom storage as an optimisation [6] [7] Identify Data reuse for building custom storage [4] G. Gutin, A. Johnstone, J. Reddington, E. Scott, and A. Yeo. An algorithm for finding input-output constrained convex sets in an acyclic digraph. J. Discrete Algorithms, 13:47 58, [5] E. Giaquinta, A. Mishra, and L. Pozzi. Maximum convex subgraphs under I/O constraint for automatic identification of custom instructions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(3): , [6] P. Biswas, N. Dutt, P. Ienne, and L. Pozzi. Automatic identification of application-specific functional units with architecturally visible storage. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages , Mar [7] M.Haaß,L.Bauer,andJ.Henkel.Automatic Custom Instruction Identification in Memory Streaming Algorithms. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pages 1 9, Oct
7 RELATED WORK 7 DATA TRANSFER IS THE BOTTLENECK Rely on source-to-source transformations [8] [9] [10] Limited Parallelism [8] [9] Large Internal Buffers [10] [8] W. Meeus and D. Stroobandt. Automating data reuse in high-level synthesis. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 1 4, Mar [9] L.-N. Pouchet, P. Zhang, P. Sadayappan, and J. Cong. Polyhedral-based data reuse optimization for configurable computing. In Proceedings of the 2013 ACM/SIGDA 21st International Symposium on Field Programmable Gate Arrays, pages 29 38, Feb [10] M. Schmid, O. Reiche, F. Hannig, and J. Teich. Loop coarsening in C-based high-level synthesis. In Proceedings of the 26th International Conference on Application-specific Systems, Architectures and Processors, pages , July 2015.
8 RELATED WORK 8 DATA TRANSFER IS THE BOTTLENECK Rely on source-to-source transformations [8] [9] [10] Limited Parallelism [8] [9] Large Internal Buffers [10] Multiple Datapaths Area efficient Accelerators [8] W. Meeus and D. Stroobandt. Automating data reuse in high-level synthesis. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 1 4, Mar [9] L.-N. Pouchet, P. Zhang, P. Sadayappan, and J. Cong. Polyhedral-based data reuse optimization for configurable computing. In Proceedings of the 2013 ACM/SIGDA 21st International Symposium on Field Programmable Gate Arrays, pages 29 38, Feb [10] M. Schmid, O. Reiche, F. Hannig, and J. Teich. Loop coarsening in C-based high-level synthesis. In Proceedings of the 26th International Conference on Application-specific Systems, Architectures and Processors, pages , July 2015.
9 METHODOLOGY 9 SW ANALYSIS FOR DATA REUSE void Sobelsystem() { outer_loop:for(i = 1; i < 100; i++) { inner_loop:for(j = 1; j < 100; j++) { Sobelmodule(image[i-1][j-1], image[i][j-1], image[i+1][j+1], image[i-1][j], image[i+1][j], image[i-1][j+1], image[i][j+1], image[i+1][j-1], image[i][j]); LOADS } } }
10 METHODOLOGY 10 SW ANALYSIS FOR DATA REUSE
11 METHODOLOGY 11 SW ANALYSIS FOR DATA REUSE
12 METHODOLOGY 12 SW ANALYSIS FOR DATA REUSE
13 METHODOLOGY 13 WINDOW 1
14 METHODOLOGY 14 WINDOW 2
15 METHODOLOGY 15 WINDOW 1 WINDOW 2 UNROLLING
16 METHODOLOGY 16 WINDOW 1 WINDOW 2 UNROLLING PIPELINING
17 METHODOLOGY 17 WINDOW 1 WINDOW 2 UNROLLING PIPELINING
18 METHODOLOGY 18 COMPILERS Perform Source Code Analysis Identify Data Reuse in Sliding Window Applications
![METHODOLOGY 19 COMPILERS Perform Source Code Analysis Identify Data Reuse in Sliding Window Applications [2] [3] [2] C. Lattner and V. Adve.](/docs-images/89/100586523/images/19-0.jpg "LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation.")
![In Proceedings of the 2nd International Symposium on Code generation and optimization, Palo Alto, California, Mar 2004. [3] T. Grosser, H.](/docs-images/89/100586523/images/19-2.jpg "Zheng, R. Aloor, A. Simbürger, A. Größlinger, and L.-N. Pouchet. Polly-polyhedral optimization in llvm.")
19 METHODOLOGY 19 COMPILERS Perform Source Code Analysis Identify Data Reuse in Sliding Window Applications [2] [3] [2] C. Lattner and V. Adve. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In Proceedings of the 2nd International Symposium on Code generation and optimization, Palo Alto, California, Mar [3] T. Grosser, H. Zheng, R. Aloor, A. Simbürger, A. Größlinger, and L.-N. Pouchet. Polly-polyhedral optimization in llvm. In Proceedings of the First International Workshop on Polyhedral Compilation Techniques (IMPACT), volume 2011, 2011.
20 METHODOLOGY 20 LLVM POLLY SCOP ANALYSIS FOR DATA REUSE WINDOW SIZE
21 METHODOLOGY 21 LLVM POLLY SCOP ANALYSIS FOR DATA REUSE STRIDE
22 METHODOLOGY 22 LLVM POLLY SCOP ANALYSIS FOR DATA REUSE FRAME SIZE
23 METHODOLOGY 23 HW IMPLEMENTATION Parameters retrieved with LLVM Polly Analysis Pass: Horizontal and Vertical Window Size Stride Iteration Domain (Frame Size)
24 METHODOLOGY 24 HW IMPLEMENTATION
25 METHODOLOGY 25 HW IMPLEMENTATION AVAILABLE INPUT DATA WIDTH
26 METHODOLOGY 26 HW IMPLEMENTATION AVAILABLE INPUT DATA WIDTH Buffer Size: Horizontal Width = Input Width (INw) INw
27 METHODOLOGY 27 HW IMPLEMENTATION Buffer Size: Horizontal Width = Input Width (INw) Example: INw INw = Horizontal Win. Size + 1
28 METHODOLOGY 28 HW IMPLEMENTATION Buffer Size: Horizontal Width = Input Width (INw) Vertical Width = Vertical Win. Size Example: INw INw = Horizontal Win. Size + 1
29 METHODOLOGY 29 HW IMPLEMENTATION Buffer Size: Horizontal Width = Input Width (INw) Vertical Width = Vertical Win. Size Example: INw INw = Horizontal Win. Size + 1
30 METHODOLOGY 30 WINDOW 1 WINDOW 2 BUFFER
31 METHODOLOGY 31 WINDOW 1 WINDOW 2 STRIDE - DISCARD TOPMOST ROW STRIDE - STORE NEW ROW
32 METHODOLOGY 32 WINDOW 1 WINDOW 2
33 METHODOLOGY 33 WINDOW 1 WINDOW 2
34 METHODOLOGY 34 WINDOW 1 WINDOW 2
35 METHODOLOGY 35 WINDOW 1 WINDOW 2
36 METHODOLOGY 36 DISPLACEMENT WINDOW 1 WINDOW 2
37 METHODOLOGY 37 DISPLACEMENT WINDOW 1 WINDOW 2 Horiz. Displacement = INw - Horiz. Win. Size + 1
38 METHODOLOGY 38 DISPLACEMENT WINDOW 1 WINDOW 2 Horiz. Displacement = INw - Horiz. Win. Size + 1 Example: INw = Horizontal Win. Size + 1 Horiz. Displacement = 2
39 EXPERIMENTAL SETUP 39 APPROACHES COMPARED ROCCC Vivado HLS Our Approach
40 EXPERIMENTAL SETUP 40 APPROACHES COMPARED ROCCC Vivado HLS Our Approach PIPELINING DATA REUSE
41 EXPERIMENTAL SETUP 41 APPROACHES COMPARED ROCCC Vivado HLS Our Approach WINDOW 1 WINDOW 2 PIPELINING PIPELINING DATA REUSE
42 EXPERIMENTAL SETUP 42 APPROACHES COMPARED ROCCC Vivado HLS Our Approach WINDOW 1 WINDOW 2 PIPELINING ROCCC PIPELINING DATA REUSE
43 EXPERIMENTAL SETUP 43 APPROACHES COMPARED ROCCC Vivado HLS Our Approach WINDOW 1 WINDOW 2 PIPELINING ROCCC PIPELINING DATA REUSE VIVADO Manual Rewrite
44 EXPERIMENTAL SETUP 44 APPROACHES COMPARED ROCCC Vivado HLS Our Approach WINDOW 1 WINDOW 2 PIPELINING ROCCC PIPELINING DATA REUSE VIVADO Manual Rewrite OUR
45 EXPERIMENTAL SETUP 45 APPROACHES COMPARED ROCCC Vivado HLS Our Approach PIPELINING DATA REUSE UNROLLING DATA REUSE ROCCC VIVADO Manual Rewrite OUR
46 EXPERIMENTAL SETUP 46 APPROACHES COMPARED ROCCC WINDOW 1 WINDOW 2 Vivado HLS Our Approach UNROLLING PIPELINING DATA REUSE UNROLLING DATA REUSE ROCCC VIVADO Manual Rewrite OUR
47 EXPERIMENTAL SETUP 47 APPROACHES COMPARED ROCCC WINDOW 1 WINDOW 2 Vivado HLS Our Approach UNROLLING PIPELINING DATA REUSE UNROLLING DATA REUSE ROCCC VIVADO Manual Rewrite OUR
48 EXPERIMENTAL SETUP 48 APPROACHES COMPARED ROCCC WINDOW 1 WINDOW 2 Vivado HLS Our Approach UNROLLING PIPELINING DATA REUSE UNROLLING DATA REUSE ROCCC VIVADO Manual Rewrite OUR
49 EXPERIMENTAL SETUP 49 APPROACHES COMPARED ROCCC WINDOW 1 WINDOW 2 Vivado HLS Our Approach UNROLLING PIPELINING DATA REUSE UNROLLING DATA REUSE ROCCC VIVADO Manual Rewrite OUR
50 EXPERIMENTAL SETUP 50 APPROACHES COMPARED ROCCC Vivado HLS Our Approach ROCCC PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH VIVADO Manual Rewrite OUR
51 EXPERIMENTAL SETUP 51 APPROACHES COMPARED INPUT WIDTH ROCCC Vivado HLS BUFFER Our Approach PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH ROCCC VIVADO Manual Rewrite OUR
52 EXPERIMENTAL SETUP 52 APPROACHES COMPARED INPUT WIDTH ROCCC Vivado HLS BUFFER Our Approach PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH ROCCC VIVADO Manual Rewrite OUR
53 EXPERIMENTAL SETUP 53 APPROACHES COMPARED INPUT WIDTH ROCCC Vivado HLS BUFFER Our Approach PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH ROCCC VIVADO Manual Rewrite OUR
54 EXPERIMENTAL SETUP 54 APPROACHES COMPARED INPUT WIDTH ROCCC Vivado HLS BUFFER Our Approach PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH ROCCC VIVADO Manual Rewrite OUR
55 EXPERIMENTAL SETUP 55 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation)
56 EXPERIMENTAL SETUP 56 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) 3 CONFIGURATIONS
57 EXPERIMENTAL SETUP 57 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) 3 CONFIGURATIONS INPUT WIDTH # DATAPATHS
58 EXPERIMENTAL SETUP 58 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) 3 CONFIGURATIONS INPUT WIDTH # DATAPATHS WINDOW SIZE SAD MAX FILTER SOBEL 4X4 8X8 3X3
59 EXPERIMENTAL SETUP 59 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) INPUT WIDTH # DATAPATHS WINDOW SIZE SINGLE DATAPATH SDP SAD MAX FILTER SOBEL 4X4 8X8 3X3
60 EXPERIMENTAL SETUP 60 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) INPUT WIDTH # DATAPATHS SAD MAX FILTER SOBEL WINDOW SIZE 4X4 8X8 3X3 SINGLE DATAPATH SDP 4, 1 8, 1 3, 1
61 EXPERIMENTAL SETUP 61 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) INPUT WIDTH # DATAPATHS WINDOW SIZE SINGLE DATAPATH SDP MULTIPLE DATAPATHS MDP SAD MAX FILTER SOBEL 4X4 8X8 3X3 4, 1 8, 1 3, 1
62 EXPERIMENTAL SETUP 62 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) INPUT WIDTH # DATAPATHS WINDOW SIZE SINGLE DATAPATH SDP MULTIPLE DATAPATHS MDP SAD 4X4 4, 1 8, 5 MAX FILTER 8X8 8, 1 16, 9 SOBEL 3X3 3, 1 8, 6
63 EXPERIMENTAL SETUP 63 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) INPUT WIDTH # DATAPATHS WINDOW SIZE SINGLE DATAPATH SDP MULTIPLE DATAPATHS MDP EXTRA MULT. DATAPATHS XMDP SAD 4X4 4, 1 8, 5 MAX FILTER 8X8 8, 1 16, 9 SOBEL 3X3 3, 1 8, 6
64 EXPERIMENTAL SETUP 64 OUR APPROACH Xilinx Virtex7 FPGA (HDL Simulation) INPUT WIDTH # DATAPATHS WINDOW SIZE SINGLE DATAPATH SDP MULTIPLE DATAPATHS MDP EXTRA MULT. DATAPATHS XMDP SAD 4X4 4, 1 8, 5 16, 13 MAX FILTER 8X8 8, 1 16, 9 24, 17 SOBEL 3X3 3, 1 8, 6 16, 14
65 EXPERIMENTS 65 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD
66 EXPERIMENTS 66 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH VIVADO_NOREW
67 EXPERIMENTS 67 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD PIPELINING DATA REUSE UNROLLING DATA REUSE PARAMETRIC I/O WIDTH VIVADO_REW Manual Rewrite
68 EXPERIMENTS 68 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD Exec. Time to process a 100x100 frame
69 EXPERIMENTS 69 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD Exec. Time to process a 100x100 frame
70 EXPERIMENTS 70 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD Exec. Time to process a 100x100 frame
71 EXPERIMENTS 71 EXECUTION TIME COMPARISON ROCCC Vivado_norew Vivado_norev Vivado_rew Vivado_rev CISC=Conf.1 SDP Conf.1========= CISC=Conf.2 Conf.2 MDP Conf.3 CISC=Conf.3 XMDP ns Sobel MaxFilter BlockSAD Exec. Time to process a 100x100 frame
72 EXPERIMENTS 72 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
73 EXPERIMENTS 73 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
74 EXPERIMENTS 74 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
75 EXPERIMENTS 75 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
76 EXPERIMENTS 76 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
77 EXPERIMENTS 77 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
78 EXPERIMENTS 78 AREA COMPARISON 45666!"""" 7,8)9$:;$.&8 7,8)9$:;$.&C!"""" 7,8)9$:.&8 7,8)9$:.&C 6<#6=6$;>?! SDP 6$;>?!=========!"""!""" MDP 6<#6=6$;>?A 6$;>?A XMDP!"" #$%&' ()*+,'-&. /'$01#23!"" #$%&' ()*+,'-&. /'$01#23 )B FLIP FLOPS LUTS
79 EXPERIMENTS 79 SPEEDUP AND AREA 74 7& & :9 ;/0,'"(0/<0,-'=>?@)A ;/0,'"(0/<0,-'=BB)A SOBEL MAX FILTER SAD SOBEL MAX FILTER SAD MDP vs Vivado_Rew!"#$%&''()%''*+(,-"./01 XMDP vs Vivado_Rew!"#$%2''()%''*+(,-"./01
80 CONCLUSIONS 80 DATA REUSE ANALYSIS BASED ON POLLY Optimize HLS of Accelerators for Sliding Window Applications Use Polly for Better HW Designs
81 CONCLUSIONS 81 DATA REUSE ANALYSIS BASED ON POLLY Optimize HLS of Accelerators for Sliding Window Applications Use Polly for Better HW Designs Exploit Data Locality
82 CONCLUSIONS 82 DATA REUSE ANALYSIS BASED ON POLLY Optimize HLS of Accelerators for Sliding Window Applications Use Polly for Better HW Designs Exploit Data Locality Design Efficient Buffers
83 CONCLUSIONS 83 DATA REUSE ANALYSIS BASED ON POLLY Optimize HLS of Accelerators for Sliding Window Applications Use Polly for Better HW Designs Exploit Data Locality Design Efficient Buffers Better Use of Resources
84 CONCLUSIONS 84 DATA REUSE ANALYSIS BASED ON POLLY Optimize HLS of Accelerators for Sliding Window Applications Use Polly for Better HW Designs Exploit Data Locality Design Efficient Buffers Better Use of Resources Better Performance
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