Multi-Gigahertz Parallel FFTs for FPGA and ASIC Implementation

Transcription

1 Multi-Gigahertz Parallel FFTs for FPGA and ASIC Implementation Doug Johnson, Applications Consultant Chris Eddington, Technical Marketing Synopsys Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA dougj@synopsys.com (949)

2 Agenda Why FPGA & Parallelism for Signal Processing? Parallel FFT Architecture Basics Design Example: 1024-pt Parallel FFT Throughput Scalability on FPGA Power reduction in ASIC Using High-Level Synthesis to Implement Parallel FFTs Summary Synopsys

3 Why FPGAs (and Parallelism)? Parallelism can achieve higher capacities than CPU or DSP processor-based implementation (Software/Firmware) Flexibility allows architecture tuning for various throughputs Lower power!! Slower clocks and reduced logic/calculation for a given throughput 1 Flexible Signal Processing Architectures Time Multicore DSP Processor Capacities 1 Dejan Markovic, Robert Brodersen, DSP Architecture Design Essentials, Springer; 2012 Synopsys

4 FPGA DSP Capacity Keeps Growing! RTL to bitfile in MINUTES RTL to Bitfile in HOURS RTL to bitfile a DAY RTL to bitfile DAYS RTL to bit file TOO LONG! Virtex-II Virtex-4 Virtex-5 Stratix-IV / Virtex DSPs, 500Mhz Stratix V ~ DSPs 760K LUT Virtex-7 ~ DSPs 1900K LUT 100K 200K 330K 760K 1M Capacity Gates, HW DSP Units & Speed, Design Effort 2M Synopsys

5 Multi-Gigahertz Challenges How to achieve multi-gigahertz throughput with device FMAX < 500Mhz? Parallel architectures! Algorithm Specification But Design Flow Difficulties: IP Availability Can I get the tuned architecture that I really need? HDL design flow expertise, architecture choices, FPGA resource mapping & QoR How do I map to the specific HW resources? Portability Which vendor/device? Capacity and Long Turnaround Times Flexible Signal Processing Architectures Synopsys

6 Parallel FFT Architecture Basics Process multiple samples at a time Radix-2 Multi-path delay commutator (MDC): throughput & pipelining Single-path delay feedback (SDF): area Radix-4 Single-path delay feedback (SDF) Multi-path delay commutator (MDC) Single-path delay commutator (SDC) Synopsys

7 Radix-2 Multi-Path Delay Commutator The most classical approach for pipeline implementation of radix-2 FFT Input sequence broken into two parallel data streams flowing forward with correct distance between data elements entering the butterfly scheduled by proper delays Synopsys

8 Implementation Using High-Level Design Created a parallel R2MDC parameterizable subsystem in Synphony Model Compiler (Simulink/MATLAB) Top-level block accepts user inputs (length, #parallel inputs, flow control, dynamic programming) and instantiates a chain of R2MDCs underneath Parallel FFT architecture based on user configuration and using a parameterized parallel radix2-mdc sub-block.... Synopsys

9 High Level System Models using Synphony Model Compiler High Quality FPGA and ASIC Design From Simulink High-Level Design & Verification in Simulink RTL RTL for multiple architectures and targets fft fft fft C S filter filter filter Synphony Model Compiler High-Level Synthesis C S B RTL Hardware Verification SMC IP Model Library C-Models for System-Level Verification High-level synthesis creates highly optimized and re-usable hardware for FPGA and ASIC Save months in verifying & validating your FPGA or ASIC system hardware Increase simulation and system validation productivity from Simulink High-level signal processing IP library for easy capture of multirate, fixed-point algorithms Use, simulate and verify RTL natively within Simulink Synopsys

10 Synphony High Level Synthesis Automated flow from higher levels of abstraction RTL Synphony IP Model Library Synphony Fixed-Point Model Simulink Simulation and Verification Synphony HLS Engine High Level Synthesis RTL RTL C-Model RTL Test bench Silicon Silicon Prototype Simulators Broad set of synthesizable signal processing functions Quickly create fixed-point algorithms Architecture optimizations and exploration: Automatic retiming/pipelining Folding for area optimizations using resource sharing & scheduling Fast, accurate speed, area, power tradeoff exploration Multi-rate clock circuit generation Choice of clocking strategies for multi-rate designs Synopsys

11 Synphony HLS Architectural Exploration Example: Exploring several digital down-converter architectures Example architectures to choose from 1. Baseline with dedicated clocks Retiming 2. Fold x1 with dedicated clocks Retiming Resource sharing turned on using system clock of factor 1X sample rates Memory extraction turned on (>128x8) 3. Fold x2 with dedicated clocks Retiming Resource sharing turned on using system clock of factor 2X sample rates Memory extraction turned on (>128x8) 4, 5, 6: Same as above but with enabled clocks Advanced Timing Engine RTL Synphony HLS Architectural Transformations and Optimizations Logic Synthesis Constraints Logic Synthesis Scripts User Constraints RTL Test bench & Script 6 example architectures Synopsys

12 Synphony High-Level Synthesis Automatic test bench generation for equivalence checking & requirements traceability VHDL or Verilog test bench automatically generated based on Simulink data. System data Inputs are used to create stimulus System data Outputs are used to generate Expected Results Bit-true proof of the VHDL/Verilog implementation equivalence vs. Simulink specification Synopsys

13 FPGA Tool Suite Implementation High-Level Synthesis Synphony Model Compiler Identify RTL Instrumentor RTL Synthesis and Analysis Logic Synthesis Logic & Physical Synthesis FPGA Synthesis & Debug Synplify Pro with HDL Analyst Synplify Premier HDL Analyst Physical Analyst VCS Simulator Simulation FPGA P&R tools Identify RTL Debugger In-System Debug Production Board FPGA-based Prototype Board (HAPS) Synopsys

14 Pipelining and Flow Control The Radix2-MDC implemented using Synphony Model Compiler has no recursive loops, thus can be pipelined to achieve fast timing It is also specifically designed to map to advanced FPGA DSP devices Stratix V, Virtex-7 Scalability is very good, but depends on FPGA fabric Synopsys

15 Lowering Power: TSMC 40nm LP Results Power tradeoff results using Synphony MC ASIC flow 2GS/S throughput held constant while varying parallelism Using activity data and Power Compiler optimization & report Parallel architectures achieve 51% lower power/frame Lower clock speeds Area penalty 250% Parallel FFT 1 FFT Throughput (Samples/s) System Clock Relative Dynamic Power 2,3 Relative Area 2 Relative Leakage Power Latency (system cycles) Parallel x2 2 GS/s 1 GHz 1X 1X Parallel x4 2 GS/s 500 MHz Parallel x8 2 GS/s 250 MHz Parallel x16 2 GS/s 125 MHz Using Synphony Model Compiler, parallel Radix2-MDC architecture and configuration as described in previous section 2. Implementation flow with Synphony Model Compiler , Design Compiler SP4 3. Dynamic power estimated using Synphony generated design and test bench of 4 frames, VCS E for activity data, and Power Compiler SP1 Synopsys

16 References [1] Dejan Markovic, Robert Brodersen, DSP Architecture Design Essentials, Springer; 2012 [2] Vladimir Stojanović, Lecture 10, Fast Fourier Transform: VLSI Architectures, course materials for Communication System Design, MIT OpenCourseWare ( Spring [3] H.e. Shousheng and M. Torkelson "A new approach to pipeline FFT processor," Parallel Processing Symposium, 1996., Proceedings of IPPS '96, The 10th International no. SN -, pp , [4] E. Wold and Alvin M. Despain "Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations," IEEE Trans. Computers vol. 33, no. 5, pp , Synopsys

17 Synopsys Thank You