MOJTABA MAHDAVI Mojtaba Mahdavi DSP Design Course, EIT Department, Lund University, Sweden

Transcription

1 High Level Synthesis with Catapult MOJTABA MAHDAVI 1

2 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 2

3 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 3

4 High Level Synthesis (HLS) Higher abstraction level. High-level synthesis bridges hardware and software domains. Generate hardware from C/C++ code or another high level language. 4

5 High Level Synthesis (HLS) A common misconception: o Synthesizing hardware from C++ provides users the freedom of describing the algorithms in any desired style of C++ coding. Remember that you are still describing hardware using a high level language! o "poor" description leads to a sub-optimal hardware. 5

6 High Level Synthesis (HLS) It is important to know HW concepts to get optimal results Successful projects require HW engineers not SW engineers o Hardware designers can work at a higher level of abstraction while creating high-performance hardware 6

7 High-Level Synthesis Benefits Develop algorithms at high level, e.g. C-level o Reduce design time o Reduce time for design changes o Easy design exploration o Faster time to market Verify at the higher level o Easier and faster verification 7

8 High-Level Synthesis Benefits Easy optimization exploration o Create multiple hardware implementation alternatives from the C source code using optimization directives Easy to maintain, easy to reuse o Create readable and portable C source code 8

9 Some Limitations Not all algorithms are suited for hardware implementations. Sequential code, control logic, large loops with function calls typically will not benefit much. 9

10 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 10

11 Catapult Catapult is a product of Mentor Graphics, which is used for high-level synthesis. Catapult takes C/C++ and System C as inputs and generates register transfer level (RTL) code. The target device can be FPGA and ASIC. 11

12 Catapult The concepts that you have learned in the DSP Design course are used in the Catapult SW o Folding/Unfolding o Re-timing/Pipelining o Bit-level optimization o and more 12

13 Catapult 13 13

14 Traditional Design Flow vs. Catapult Flow 14

15 Top-level Design Similar to RTL designs, HLS needs to know the "top" level of your design. o The highest level of your design Top Module Top module specifies: o The design interfaces with the outside world o Port definitions, direction, bit widths, and data types Input Ports Block 1 Block 2 Block 3 Memory Output Ports 15

16 Registered Outputs In general, high-level synthesis builds synchronous designs by default. All outputs of the top-level design are registered o To guarantee that timing is met when connecting to another design 16

17 Design Example Consider the following simple design as an example to introduce: o The concepts in HLS process o The corresponding step in Catapult design flow 17

18 Port Width Port Direction Bit widths of the top-level ports, excluding clock and reset, are implied by the data type. The port direction is implied by how an interface variable is used in the C++ code. 18

19 Control Ports C++ code has no concept of timing. There are no clocks, enables, or resets described in the design source files. o These signals are added by the synthesis tool. Control over things like polarity, type of reset, etc, are taken care by setting design constraints. 19

20 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 20

21 Data Types Two important data types: o int, ac_int o ac_fixed To use these data types the following header files should be included in the design source files: o ac_int.h o ac_fixed.h It is possible to define user data types. 21

22 Data Types 22

23 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 23

24 Create a New Project 24

25 Create a New Project 25

26 Create a New Design File 26

27 Add Input Files 27

28 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 28

29 Set Top Module 29

30 Design Setup 30

31 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 31

32 Data Flow Graph Analysis HLS process starts by analyzing the data dependencies between the various steps in the algorithm. The analysis leads to a Data Flow Graph (DFG). 32

33 Design Example Data dependencies and the order of operations are specified by the connection between nodes. 33

34 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 34

35 Resource Allocation Each operation in the extracted DFG is mapped onto a hardware resource. o Each resource corresponds to a physical implementation of the operator in hardware. Some operators may have multiple hardware resource implementations o Different area, delay, and latency specifications. Timing and area constraints will be applied to this implementation. 35

36 Resource Allocation All resources are selected from a technology specific pre-characterized library o Library is already determined in Design Setup step 36

37 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 37

38 Scheduling HLS adds "time" to the design during the "scheduling step. Scheduling determines that each operation in the DFG should be performed in which clock cycle. o So, based on a target clock frequency, registers should be added between operations. 38

39 Scheduling This process is similar to technique what RTL designers would call pipelining o Inserting registers to reduce combinational delays. Note that this is not the same as "loop pipelining" which is discussed later. 39

40 Scheduling Consider that in our design example: o "add" operation takes 3 ns o Clock period equals 5 ns Each add operation is scheduled in its own clock cycle C1, C2, and C3 o Registers are inserted automatically between each adder. 40

41 Timing Constraints 41

42 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 42

43 Hardware Implementation The corresponding hardware that is generated from the schedule varies depending on how the design is constrained in terms of: o Resource allocation o The amount of loop pipelining 43

44 Loop Pipelining "Loop Pipelining" allows a new iteration of a loop to be started before the current iteration has finished. o Execution of the loop iterations to be overlapped o Increasing the design performance by running loops in parallel The top-level function call has an implied loop, also known as the main loop. o Each iteration of the implied loop corresponds to execution of the schedule 44

45 Initiation Interval (II) The amount of overlap between the loops is determined by the "Initiation Interval (II)". o Specifies the number of pipeline stages 45

46 Case1: No Pipelining Design is left unconstrained o There is only a single pipeline stage o No overlap between execution of each iteration of main loop Data will be written every four clock cycles o Latency of three clock cycles o Throughput of four clock cycles 46

47 Case1: No Pipelining There is no overlap between any operation. Resulting hardware uses a single adder to accumulate a, b, c, and d. Reduction in the overall area. 47

48 Case 2: Pipelining with II = 1 Pipelining with an II=1 results in a new iteration started every clock cycle. o Latency of 3 clock cycles o Throughput of 1 Three adders are required in hardware since all three pipeline stages can be active at the same time. o More area 48

49 Case 2: Pipelining with II = 1 Iteration one is started in C2 and iteration 2 is started in C3. 49

50 Architecture Specification 50

51 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 51

52 Design Schedule 52

53 Design Synthesis 53

54 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 54

55 Design Schematic 55

56 Design Schematic 56

57 Result Analysis 57

58 HDL Generation 58

59 Outline High Level Synthesis HLS Design Flow in Catapult Data Types Project Creation Design Setup Data Flow Analysis Resource Allocation Scheduling Architecture Mapping Synthesis Result Analysis Design Verification 59

60 Test Bench o Include your design source file o Call your design o Generate inputs to the design o Write outputs in the console 60

61 Design Verification SCVerify flow in Catapult automatically generates the verification infrastructure. o The functionality of the HLS generated RTL against the users original source code will be verified. SCVerify supports Mentor QuestaSim/ModelSim, Synopsys VCS and Cadence IUS/NCSim simulation environments. 61

62 Design Verification 62

63 Design Verification 63

64 64