14:332:331. Computer Architecture and Assembly Language Fall Week 5

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1 14:3:331 Computer Architecture and Assembly Language Fall 2003 Week 5 [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] 331 W05.1 Spring 2005

2 Head s Up This week s material Introduction to VHDL - Reading assignment Y, Chapters 1 through 3 Next week s material VHDL modeling - Reading assignment Y, Chapter 4 and 5 MIPS arithmetic operations - Reading assignment PH 4.1 through W05.2 Spring 2005

3 To make the architect s crucial task even conceivable, it is necessary to separate the architecture, the definition of the product as perceivable by the user, from its implementation. Architecture versus implementation defines a clean boundary between parts of the design task, and there is plenty of work on each side of it. The Mythical Man-Month, Brooks, pg W05.3 Spring 2005

4 Review: MIPS ISA Category Instr Op Code Example Meaning Arithmetic (R & I format) Data Transfer (I format) add 0 and add $s1, $s2, $s3 $s1 = $s2 + $s3 subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3 add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6 or immediate 13 ori $s1, $s2, 6 $s1 = $s2 v 6 load word 35 lw $s1, 24($s2) $s1 = Memory($s2+24) store word 43 sw $s1, 24($s2) Memory($s2+24) = $s1 load byte lb $s1, 25($s2) $s1 = Memory($s2+25) store byte 40 sb $s1, 25($s2) Memory($s2+25) = $s1 Cond. Branch (I & R format) Uncond. Jump (J & R format) load upper imm 15 lui $s1, 6 $s1 = 6 * 2 16 br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L br on not equal 5 bne $s1, $s2, L if ($s1!=$s2) go to L set on less than 0 and 42 slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0 set on less than immediate 10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else $s1=0 jump 2 j 2500 go to jump register 0 and 8 jr $t1 go to $t1 jump and link 3 jal 2500 go to 10000; $ra=pc W05.4 Spring 2005

5 Review: MIPS Organization, so far src1 addr src2 addr dst addr write data Processor Register File registers ($zero - $ra) bits src1 data src2 data read/write addr Memory words Exec br offset PC Add 4 Fetch PC = PC+4 Decode Add ALU read data write data byte address (big Endian) bits word address (binary) 331 W05.5 Spring 2005

6 Processor Organization Processor control needs to have the Ability to input instructions from memory Logic to control instruction sequencing and to issue signals that control the way information flows between the datapath components and the operations performed by them Processor datapath needs to have the Ability to load data from and store data to memory Interconnected components - functional units (e.g., ALU) and storage units (e.g., Register File) - for executing the ISA Need a way to describe the organization High level (block diagram) description Schematic (gate level) description Textural (simulation/synthesis level) description 331 W05.6 Spring 2005

7 Levels of Description of a Digital System Architectural models programmer's view at a high level; written in your favorite programming language Functional/Behavioral Register Transfer Logic more detailed model, like the block diagram view model is in terms of datapath FUs, registers, busses; register xfer operations are clock phase accurate model is in terms of logic gates; delay information can be specified for gates; digital waveforms Less Abstract More Accurate Slower Simulation Circuit model is in terms of circuits (electrical behavior); accurate analog waveforms Schematic capture + logic simulation package like LogicWorks Special languages + simulation systems for describing the inherent parallel activity in hardware (VHDL and verilog) 331 W05.7 Spring 2005

8 Why Simulate First? Physical breadboarding discrete components/lower scale integration precedes actual construction of the prototype verification of the initial design No longer possible as designs reach higher levels of integration! Simulation before construction - aka functional verification high level constructs means faster to design and test can play what if more easily limited performance (can t usually simulate all possible input transitions) and accuracy (can t usually model wiring delays accurately), however 331 W05.8 Spring 2005

9 VHDL (VHSIC Hardware Description Language) Goals: Support design, documentation, simulation & verification, and synthesis of hardware Allow integrated design at multiple levels - behavioral and structural (gate level) Concepts: Design entity-architecture descriptions Time-based execution (discrete event simulation) model Design Entity-Architecture == Hardware Component Entity == External Characteristics Architecture (Body ) == Internal Behavior or Structure 331 W05.9 Spring 2005

10 Entity Interface Externally visible characteristics Ports: channels of communication - (inputs, outputs, clocks, control) Generic parameters: define class of components - (timing characteristics, size, fan-out) entity name_of_component is port(a,b: in std_logic; y: out std_logic); end name_of_component; 331 W05.10 Spring 2005

11 Architecture Body Internal behavior or structure of circuit Declaration of module s internal signals Description of behavior of circuit - concurrent behavioral description - collection of Concurrent Signal Assignment (CSA) statements executed concurrently - process behavioral description - CSAs and variable assignment statements within a process description - structural description - system described in terms of the interconnections of its components architecture behavioral of name_of_component is signal s1,s2: std_logic; begin - description of behavior of ports and signals; end behavioral; 331 W05.11 Spring 2005

12 VHDL Example: nor-nor gate a b c t0 y entity nor_nor_logic is port (a,b,c: in std_logic; y: out std_logic); end nor_nor_logic; architecture concurrent_behavior of nor_nor_logic is signal t0: std_logic; begin t0 <= a nor b; y <= t0 nor c; end concurrent_behavior; 331 W05.12 Spring 2005

13 Things to Notice <= indicates a Concurrent Signal Assignment (CSA) like real logic, nor_nor process is in an infinite loop t0 and y are signals, not variables they change when ever the inputs (a, b, or c) change std_logic conforms to the IEEE 1164 standard library IEEE; use IEEE.std_logic_1164.all; entity nor_nor_logic is... U UNINITIALIZED X Forcing unknown 0 Forcing 0 1 Forcing 1 Z High impedance W Weak unknown L Weak 0 H Weak 1 - Don t care 331 W05.13 Spring 2005

14 Modeling Delays Can model temporal, as well as functional behavior, with delays in CSAs t0 changes 1 ns after a or b changes entity nor_nor_logic is port (a,b,c: in std_logic; y: out std_logic); end nor_nor_logic; architecture concurrent_behavior of nor_nor_logic is signal t0: std_logic; begin t0 <= (a nor b) after 1 ns; y <= (t0 nor c) after 1 ns; end concurrent_behavior; 331 W05.14 Spring 2005

15 Waveforms and Timing a b c t0 y abc t0 y 1 ns 331 W05.15 Spring 2005

16 Review: VHDL Goals: Support design, documentation, simulation & verification, and synthesis of hardware Allow integrated design at multiple levels - behavioral and structural (gate level) Concepts: Design entity-architecture descriptions Time-based execution (discrete event simulation) model Design Entity-Architecture == Hardware Component Entity == External Characteristics Architecture (Body ) == Internal Behavior or Structure 331 W05.16 Spring 2005

17 Review: An Entity-Architecture Example a b c t0 y entity nor_nor_logic is port(a,b,c: in std_logic; y: out std_logic); end nor_nor_logic; architecture concurrent_behavior of nor_nor_logic is signal t0: std_logic; begin t0 <= (a nor b) after 1 ns; y <= (t0 nor c) after 1 ns; end concurrent_behavior; 331 W05.17 Spring 2005

18 Entity-Architecture Features Entity defines externally visible characteristics Ports: channels of communication - signal names for inputs, outputs, clocks, control Generic parameters: define class of components - timing characteristics, size (fan-in), fan-out Architecture defines the internal behavior or structure of circuit Declaration of internal signals Description of behavior - concurrent behavioral description: collection of Concurrent Signal Assignment (CSA) statements (indicated by <=) executed concurrently; can also model temporal behavior with the delay annotation - process behavioral description: CSAs and variable assignment statements within a process description - structural description: system described in terms of the interconnections of its components 331 W05.18 Spring 2005

19 New Object: Signals Digital systems are about signals, not variables signal <= value expressions after time expression signals are analogous to wires and change when ever their inputs change - time-value pairs resulting in a waveform std_logic conforms to the 9-value IEEE 1164 standard for signals When a signal has multiple drivers (e.g., a bus), the value of the resulting signal is determined by a resolution function for std_logic and std_logic_vector the resolution function (lookup table) is provided by std_logic_1164 package U UNINITIALIZED X Forcing unknown 0 Forcing 0 1 Forcing 1 Z High impedance W Weak unknown L Weak 0 H Weak 1 - Don t care 331 W05.19 Spring 2005

20 Model of Execution CSA s are executed concurrently - textural order of the statements is irrelevant to the correct operation Two stage model of circuit execution first stage - all CSA s with events occurring at the current time on signals on their right hand side (RHS) are evaluated - all future events that are generated from this evaluation are scheduled on the events list second stage - time is advanced to the time of the next event VHDL programmer specifies events - with CSA s delays - with CSA s with delay annotation concurrency - by having a distinct CSA for each signal 331 W05.20 Spring 2005

21 Constant Objects Constant parameters provide default values may be overridden on each instance attach value to symbol as attribute entity nor_nor_logic is port(a,b,c: in std_logic; y: out std_logic); end nor_nor_logic; architecture concurrent_behavior of nor_nor_logic is signal t0: std_logic; constant gate_delay: Time := 1 ns; begin t0 <= (a nor b) after gate_delay; y <= (t0 nor c) after gate_delay; end concurrent_behavior; 331 W05.21 Spring 2005

22 Bit-Vector Data Types Std_logic_vector (31 downto 0) is equivalent to a -bit bus Can convert it to a bit integer entity nand is port(a,b: in std_logic_vector (31 downto 0); y: out std_logic_vector (31 downto 0)); end nand; architecture concurrent_behavior of nand is begin y <= a nand b; end concurrent_behavior; Analyzer (compiler) expands the architecture into 2-input nand gates with the inputs connected appropriately 331 W05.22 Spring 2005

23 Conditional Signal Assignment Statement Conditional CSA order is important - the first conditional expression that evaluates to true determines the output signal entity mux4 is In1 port(in0,in1,in2,in3: in In2 std_logic_vector (7 downto 0); In3 S0,S1: in std_logic; Z: out std_logic_vector (7 downto 0)); end mux4; In0 S S1 Z architecture behavior of mux4 is begin Z <= In0 after 5 ns when S0 = 0 and S1 = 0 else In1 after 5 ns when S0 = 0 and S1 = 1 else In2 after 5 ns when S0 = 1 and S1 = 0 else In3 after 5 ns when S0 = 1 and S1 = 1 else after 5 ns end behavior; 331 W05.23 Spring 2005

24 Selected Signal Assignment Statement Selected CSA all choices are evaluated, but only one must be true entity reg_file is port(addr1,addr2: in std_logic_vector (1 downto 0); dout1, dout2: out std_logic_vector (31 downto 0)); end reg_file; architecture behavior of reg_file is signal reg0: std_logic_vector (31 downto 0) := to_stdlogicvector (x ); signal reg1,reg2: std_logic_vector (31 downto 0) := to_stdlogicvector (x ffffffff ); begin with addr1 select dout1 <= reg0 after 5 ns when 00, <= reg1 after 5 ns when 01, <= reg2 after 5 ns when others; with addr2 select dout2 <= reg0 after 5 ns when 00, <= reg1 after 5 ns when 01, <= reg2 after 5 ns when others; end behavior; 331 W05.24 Spring 2005

25 Summary Introduction to VHDL A language to describe hardware - entity = symbol, architecture ~ schematic, signals = wires Inherently concurrent (parallel) Has time as concept Behavioral descriptions of a component - can be specified using CSAs - can be specified using one or more processes and sequential statements Structural descriptions of a system are specified in terms of its interconnections - behavioral models of each component must be provided 331 W05.25 Spring 2005

Computer Architecture

CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,