ECE 699: Lecture 12. Introduction to High-Level Synthesis

Transcription

1 ECE 699: Lecture 12 Introduction to High-Level Synthesis

2 Required Reading The ZYNQ Book Chapter 14: Spotlight on High-Level Synthesis Chapter 15: Vivado HLS: A Closer Look S. Neuendorffer and F. Martinez-Vallina, Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 2013 Tutorial

3 Recommended Reading G. Martin and G. Smith, High-Level Synthesis: Past, Present, and Future, IEEE Design & Test of Computers, IEEE, vol. 26, no. 4, pp , July Vivado Design Suite Tutorial, High-Level Synthesis, UG871, Nov Vivado Design Suite User Guide, High-Level Synthesis, UG902, Oct Introduction to FPGA Design with Vivado High-Level Synthesis, UG998, Jul

4 Behavioral Synthesis I/O Behavior Algorithm Target Library Behavioral Synthesis RTL Design Logic Synthesis Classic RTL Design Flow Gate level Netlist 4

5 Need for High-Level Design Higher level of abstraction Modeling complex designs Reduce design efforts Fast turnaround time Technology independence Ease of HW/SW partitioning 5

6 Platform Mapping SW/HW Partitioning Program Software (executed in the microprocessor system) Hardware (executed in the reconfigurable processor system) ECE 448 FPGA and ASIC Design with VHDL 6

7 SW/HW Partitioning & Coding Traditional Approach Specification SW/HW Partitioning SW Coding HW Coding SW Compilation HW Compilation SW Profiling HW Profiling ECE 448 FPGA and ASIC Design with VHDL 7

8 SW/HW Partitioning & Coding New Approach Specification SW/HW Coding SW/HW Partitioning SW Compilation HW Compilation SW Profiling HW Profiling ECE 448 FPGA and ASIC Design with VHDL 8

9 Advantages of Behavioral Synthesis Easy to model higher level of complexities Smaller in size source compared to RTL code Generates RTL much faster than manual method Multi-cycle functionality Loops Memory Access 9

10 Short History of High-Level Synthesis Generation 1 (1980s-early 1990s): research period Generation 2 (mid 1990s-early 2000s): Commercial tools from Synopsys, Cadence, Mentor Graphics, etc. Input languages: behavioral HDLs Outcome: Commercial failure Generation 3 (from early 2000s): Target: ASIC Domain oriented commercial tools: in particular for DSP Input languages: C, C++, C-like languages (Impulse C, Handel C, etc.), Matlab + Simulink, Bluespec Target: FPGA, ASIC, or both Outcome: First success stories 10

11 Hardware-Oriented High-Level Languages C-Based System level languages Commercial Handel C -- Celoxica Ltd. Impulse C -- Impulse Accelerated Technologies Carte C SRC Computers SystemC -- The Open SystemC Initiative Research Streams-C -- Los Alamos National Laboratory SA-C -- Colorado State University, University of California, Riverside, Khoral Research, Inc. SpecC University of California, Irvine and SpecC Technology Open Consortium 11

12 Other High-Level Design Flows Matlab-based AccelChip DSP Synthesis -- AccelChip System Generator for DSP -- Xilinx GUI Data-Flow based Corefire -- Annapolis Microsystems Java-based Commercial Forge -- Xilinx Research JHDL Brigham Young University 12

13 Handel-C Overview High-level language based on ISO/ANSI-C for the implementation of algorithms in hardware Allows software engineers to design hardware without retraining Clean extensions for hardware design including flexible data widths, parallelism and communications Well defined timing model Each statement takes a single clock cycle Includes extended operators for bit manipulation, and high-level mathematical macros (including floating point) 13

14 Handel-C/ANSI-C Comparisons ANSI-C HANDEL-C Recursion ANSI-C Standard Library Floa=ng Point Preprocessors i.e. #define Pointers Structures ANSI-C Constructs for, while, if, switch Arithme=c operators Func=ons Arrays Bitwise logical operators Logical operators Handel-C Standard Library Signals Parallelism Interfaces Arbitrary width variables Enhanced bit manipula=on RAM, ROM 14

15 Handel-C Design Flow Executable Specifica=on Handel-C VHDL Synthesis EDIF EDIF Place & Route 15

16 Different Levels of C/C++ Synthesis Abstraction Untimed C Domain (Non-implementation-specific) More abstract, less implementationspecific Pure C/C++ Timed C Domain (Implementation-specific) SystemC Augmented C/C++ RTL Domain (Implementation-specific) Verilog and VHDL Less abstract, more implementationspecific The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 16

17 Pure Untimed C/C++ Design Flow User interaction and guidence Verilog / VHDL RTL RTL Synthesis Gate-level netlist Pure C/C++ Pure C/C++ Synthesis ASIC target FPGA target Auto-generated, implementation-specific - Non-implementation-specific - Easy to create - Fast to simulate - Easy to modify Verilog / VHDL RTL RTL Synthesis LUT/CLBlevel netlist The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 17

18 Catapult C ( ) Calypto Design Systems ( ) (2015-present) 18

19 Catapult C Catapult C automatically converts un-timed C/C++ descriptions into synthesizable RTL. ECE 448 FPGA and ASIC Design with VHDL 19

20 SystemC -based design-flow alternatives Implementation specific, relatively slow to simulate, relatively difficult to modify SystemC Auto-RTL Translation Verilog / VHDL RTL RTL Synthesis SystemC Synthesis Gate-level netlist Alternative SystemC flows 20

21 SystemC Evolution System Untimed Algorithmic Behavioral/ Transactionlevel RTL SystemC 1.0 SystemC 2.0 Timed The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 21

22 Reconfigurable Supercomputers ECE 448 FPGA and ASIC Design with VHDL 22

23 What is a Reconfigurable Computer? Microprocessor system Reconfigurable system µp... µp FPGA... FPGA µp memory... µp memory FPGA memory... FPGA memory I/O Interface Interface I/O ECE 448 FPGA and ASIC Design with VHDL 23

24 Reconfigurable Supercomputers Machine SRC 6 from SRC Computers Cray XD1 from from Cray SGI Altix from SGI SRC 7 from SRC Computers, Inc, Released

25 Pros and cons of reconfigurable computers + can be programmed using high-level programming languages, such as C, by mathematicians & scientist themselves + facilitates hardware/software co-design + shortens development time, encourages experimentation and complex optimizations + allows sharing costs among users of various applications - high entry cost (~$100,000) - hardware aware programming - limited portability - limited availability of libraries - limited maturity of tools 25

26 SRC Programming Model Microprocessor main.c function_1() function_2() ANSI C function_1 macro_1(a, b, c) macro_2(b, d) macro_2(c, e) function_2 macro_3(s, t) macro_1(n, b) macro_4(t, k) FPGA MAP C (subset of ANSI C) Libraries of macros macro_1 macro_2 macro_3 macro_4. VHDL FPGA I/O a Macro_1 b c Macro_2 Macro_2 d e I/O 26

27 SRC Compilation Process Application sources Macro sources.c or.f files.mc or.mf files. vhd or.v files HDL sources.v files Logic synthesis µp Compiler MAP Compiler Netlists. ngo files Object files.o files.o files Place & Route Linker Application executable.bin files Configuration bitstreams 27

28 Library Development - SRC LLL (ASM) HLL (C, Fortran) HLL (C, Fortran) µp system FPGA system HDL (VHDL, Verilog) HLL (C, Fortran) Library Developer HLL (C, Fortran) Application Programmer 28

29 SRC Programming Environment + very easy to learn and use + standard ANSI C + hides implementation details + very well integrated environment + mature - subset of C - legacy C code requires rewriting - C limitations in describing HW (paralellism, data types) - closed environment, limited portability of code to HW platforms other than SRC 29

30 Application Development for Reconfigurable Computers Program Entry Platform mapping Debugging & Verification Compilation Execution 30

31 Ideal Program Entry Function Program Entry ECE 448 FPGA and ASIC Design with VHDL 31

32 Actual Program Entry Preferred Architectures Function SW/HW Partitioning Use of FPGA Resources (multipliers, µp cores) Sequence of Run-time Reconfigurations Program Entry FPGA Mapping Data Transfers & Synchronization SW/HW Interface Use of Internal and External Memories 32

33 Cinderella Story AutoESL Design Technologies, Inc. (25 employees) Flagship product: AutoPilot, translating C/C++/System C to VHDL or Verilog Acquired by the biggest FPGA company, Xilinx Inc., in 2011 AutoPilot integrated into the primary Xilinx toolset, Vivado, as Vivado HLS, released in 2012 High-Level Synthesis for the Masses 33

34 Vivado HLS High Level Language C, C++, System C Vivado HLS Hardware Description Language VHDL or Verilog

35 HLS-Based Development and Benchmarking Flow Reference ImplementaAon in C Manual Modifications (pragmas, tweaks) HLS-ready C code Test Vectors High-Level Synthesis Post Place & Route Results HDL Code Physical Implementation FPGA Tools Netlist Functional Verification Timing Verification

36 LegUp Academic Tool for HLS Open-source HLS Tool Developed at the University of Toronto Faculty supervisors: Jason H. Anderson and Stephen Brown FPL Community Award 2014 High-Level Synthesis from C to Verilog Targets Altera FPGAs (extension to Xilinx relatively simple) Two flows Pure Hardware Hardware/Software Hybrid = Tiger MIPS + hardware accelerator(s) + Avalon bus + shared on-chip and off-chip memory 36

37 Cryptol New Language for Cryptology Domain specific language for cryptology: Cryptol High-level programming language similar to Haskell Developed by Galois Inc. based in Portland, USA High-Level Synthesis from Cryptol to efficient Software and Hardware Reference C Modified C Cryptol Optimized C HLS SW HLS HW HLS HDL Optimized C HDL SW benchmarking HW benchmarking SW benchmarking HW benchmarking 37

38 Levels of Abstraction in FPGA Design Source: The Zynq Book

39 High-Level Synthesis vs. Logic Synthesis Source: The Zynq Book

40 Algorithm and Interface Synthesis Source: The Zynq Book

41 Vivado HLS Design Flow Source: The Zynq Book

42 Design Trade-offs Explored Using HLS Source: The Zynq Book

43 C Functional Verification and C/RTL Cosimulation in Vivado HLS Source: The Zynq Book

44 Vivado HLS

45 Vivado HLS Scheduling and Binding Source: The Zynq Book

46 Vivado HLS Scheduling and Binding Scheduling translation of the RTL statements interpreted from the C code into a set of operations, each with an associated duration in terms of clock cycles. Affected by the clock frequency, uncertainty, target technology, and user directives. Binding - associating the scheduled operations with the physical resources of the target device. Source: The Zynq Book

47 Three Possible Outcomes from HLS Average of 10 numbers Source: The Zynq Book

48 Vivado HLS Synthesis Process Source: The Zynq Book