L6: FSMs and Synchronization

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1 L6: FSMs ad Sychroizatio Ackowledgemets: Materials i this lecture are courtesy of the followig sources ad are used with permissio. Rex Mi J. Rabaey, A. Chadrakasa, B. Nikolic. igital Itegrated Circuits: A esig Perspective. Pretice Hall/Pearso, 23.

2 Asychroous Iputs i Sequetial Systems What about exteral sigals? Clock Sequetial System Ca t guaratee setup ad hold times will be met! Whe a asychroous sigal causes a setup/hold violatio... Clock Trasitio is missed o first clock cycle, but caught o ext clock cycle. I II III Trasitio is caught o first clock cycle. Courtesy of Natha Ickes. Used with permissio. Output is metastable for a idetermiate amout of time. : Which cases are problematic? 2?

3 Asychroous Iputs i Sequetial Systems All of them ca be, if more tha oe happes simultaeously withi the same circuit. Idea: esure that exteral sigals directly feed exactly oe flip-flop Sequetial System Asyc Iput Clocked Sychroous System Clock Clock Clock Courtesy of Natha Ickes. Used with permissio. This prevets the possibility of I ad II occurrig i differet places i the circuit, but what about metastability? 3

4 Hadlig Metastability Prevetig metastability turs out to be a impossible problem High gai of digital devices makes it likely that metastable coditios will resolve themselves quickly Solutio to metastability: allow time for sigals to stabilize Likely to be metastable right after samplig Very ulikely to be metastable for > clock cycle Extremely ulikely to be metastable for >2 clock cycle Complicated Sequetial System Clock How may registers are ecessary? eps o may desig parameters(clock speed, device speeds, ) I 6., oe or maybe two sychroizatio registers is sufficiet 4

5 Fiite State Machies Fiite State Machies (FSMs) are a useful abstractio for sequetial circuits with cetralized states of operatio At each clock edge, combiatioal logic computes outputs ad ext state as a fuctio of iputs ad preset state iputs + preset state Combiatioal outputs + ext state Flip- Flops 5

6 Two Types of FSMs Moore ad Mealy FSMs are distiguished by their output geeratio Moore FSM: iputs x...x Comb. ext state S + Flip- Flops Comb. outputs y k = f k (S) preset state S Mealy FSM: iputs x...x Comb. direct combiatioal path! S + Flip- Flops Comb. outputs y k = f k (S, x...x ) S 6

7 esig Example: Level-to to-pulse A level-to-pulse coverter produces a sigle-cycle pulse each time its iput goes high. I other words, it s a sychroous risigedge detector. Sample uses: Buttos ad switches pressed by humas for arbitrary periods of time Sigle-cycle eable sigals for couters Wheever iput L goes from low to high... L Level to Pulse Coverter P...output P produces a sigle pulse, oe clock period wide. 7

8 State Trasitio iagrams Block diagram of desired system: Sychroizer Edge etector usychroized user iput L Level to Pulse FSM P State trasitio diagram is a useful FSM represetatio ad desig aid if L= at the clock edge, the jump to state. L= L= Biary values of states L= if L= at the clock edge, the stay i state. Low iput, Waitig for rise P = L= Edge etected! P = L= High iput, Waitig for fall P = L= This is the output that results from this state. (Moore or Mealy?) 8

9 erivatio for a Moore FSM Trasitio diagram is readily coverted to a state trasitio table (just a truth table) Curret State I Next State Out L= Low iput, Waitig for rise P = L= L= L= Edge etected! P = L= High iput, Waitig for fall P = L= S S L S + S + P Combiatioal logic may be derived by Karaugh maps for S + : S S L X X for S + : S S L X X L Comb. S + = LS S + = L S + S Flip- Flops Comb. P = S S P S S for P: X 9

10 Moore Level-to to-pulse Coverter iputs x...x Comb. ext state S + Flip- Flops Comb. outputs y k = f k (S) S + = LS S + = L preset state S P = S S Moore FSM circuit implemetatio of level-to-pulse coverter: L S + S P S + S

11 esig of a Mealy Level-to to-pulse direct combiatioal path! Comb. S + Flip- Flops Comb. S Sice outputs are determied by state ad iputs, Mealy FSMs may eed fewer states tha Moore FSM implemetatios. Whe L= ad S=, this output is asserted immediately ad util the state trasitio occurs (or L chages). L= P= Iput is low L= P= Iput is high L P Clock State 2 L= P= 2. After the trasitio to S= ad as log as L remais at, this output is. L= P= Output trasitios immediately. State trasitios at the clock edge.

12 Mealy Level-to to-pulse Coverter L= P= Iput is low L= P= L= P= Iput is high L= P= Pres. State S I L Next State S + Out P Mealy FSM circuit implemetatio of level-to-pulse coverter: L S + S P S FSM s state simply remembers the previous value of L Circuit beefits from the Mealy FSM s implicit sigle-cycle assertio of outputs durig state trasitios 2

13 Moore/Mealy Trade-Offs Remember that the differece is i the output: Moore outputs are based o state oly Mealy outputs are based o state ad iput Therefore, Mealy outputs geerally occur oe cycle earlier tha a Moore: Moore: delayed assertio of P L P Clock State[] Mealy: immediate assertio of P L P Clock State Compared to a Moore FSM, a Mealy FSM might... Be more difficult to coceptualize ad desig Have fewer states 3

14 Review: FSM Timig Requiremets Timig requiremets for FSM are idetical to ay geeric sequetial system with feedback Miimum Clock Period Miimum elay iputs + preset state Combiatioal T logic outputs + ext state iputs + preset state Combiatioal T logic,cd outputs + ext state T cq T cq,cd Flip- Flops T su Flip- Flops T hold T T > T cq + T logic + T su T cq,cd + T logic,cd > T hold 4

The 6. Vig Machie Lab assistats demad a ew soda machie for the 6. lab. You desig the FSM cotroller. All selectios are $.3. The machie makes chage. (imes ad ickels oly.

15 The 6. Vig Machie Lab assistats demad a ew soda machie for the 6. lab. You desig the FSM cotroller. All selectios are $.3. The machie makes chage. (imes ad ickels oly.) Iputs: limit per clock - quarter iserted - dime iserted N - ickel iserted Outputs: limit per clock C - dispese ca - dispese dime N - dispese ickel 3 3 COINS ONLY 25 5 Co Sprite Jolt Water LS63 5

16 What States are i the System? A startig (idle) state: idle A state for each possible amout of moey captured: got5c gotc got5c... What s the maximum amout of moey captured before purchase? 25 cets (just shy of a purchase) + oe quarter (largest coi)... got35c got4c got45c got5c States to dispese chage (oe per coi dispesed): got45c ispese ime ispese Nickel 6

17 A Moore Ver Here s a first cut at the state trasitio diagram. = N= idle got5c N= = gotc = N= = got5c N= = = got2c See a better way? So do we. o t go away... = = N= got25c N= got3c C= got35c C= got4c C= got45c C= = = = chg35 N= chg4 = chg45 = chg45b N= got5c C= chg5 = chg5b = 7

18 State Reductio = = = N= N= N= N= idle got5c gotc got5c = = uplicate states have: The same outputs, ad The same trasitios There are two duplicates i our origial diagram. = = = = N= N= N= N= idle got5c gotc got5c got2c = = = = = N= got2c got25c N= got3c C= got35c C= got4c C= got45c C= got5c C= = = = chg35 N= chg4 = chg45 = chg5 = chg45b N= chg5b = 7 states 5 state bits 5 states 4 state bits = = N= got25c N= got3c C= got35c C= got4c C= got45c C= got5c C= = = = rt5 N= rt = rt5 = rt2 = 8

19 Verilog for the Moore Ver Comb. State Register Comb. module moorever (N,,, C, N,, clk, reset, state); iput N,,, clk, reset; output C, N, ; output [3:] state; reg [3:] state, ext; States defied with parameter keyword FSMs are easy i Verilog. Simply write oe of each: State register (sequetial always block) Next-state combiatioal logic (comb. always block with case) Output combiatioal logic block (comb. always block or assig statemets) parameter ILE = ; parameter GOT_5c = ; parameter GOT_c = 2; parameter GOT_5c = 3; parameter GOT_2c = 4; parameter GOT_25c = 5; parameter GOT_3c = 6; parameter GOT_35c = 7; parameter GOT_4c = 8; parameter GOT_45c = 9; parameter GOT_5c = ; parameter RETURN_2c = ; parameter RETURN_5c = 2; parameter RETURN_c = 3; parameter RETURN_5c = 4; State register defied with sequetial always block (posedge clk or egedge reset) if (!reset) state <= ILE; else state <= ext; 9

20 Verilog for the Moore Ver Next-state logic withi a combiatioal always block (state or N or or ) begi case (state) ILE: if () ext = GOT_25c; else if () ext = GOT_c; else if (N) ext = GOT_5c; else ext = ILE; GOT_5c: if () ext = GOT_3c; else if () ext = GOT_5c; else if (N) ext = GOT_c; else ext = GOT_5c; GOT_c: if () ext = GOT_35c; else if () ext = GOT_2c; else if (N) ext = GOT_5c; else ext = GOT_c; GOT_5c: if () ext = GOT_4c; else if () ext = GOT_25c; else if (N) ext = GOT_2c; else ext = GOT_5c; GOT_2c: if () ext = GOT_45c; else if () ext = GOT_3c; else if (N) ext = GOT_25c; else ext = GOT_2c; GOT_25c: if () ext = GOT_5c; else if () ext = GOT_35c; else if (N) ext = GOT_3c; else ext = GOT_25c; GOT_3c: ext = ILE; GOT_35c: ext = RETURN_5c; GOT_4c: ext = RETURN_c; GOT_45c: ext = RETURN_5c; GOT_5c: ext = RETURN_2c; RETURN_2c: ext = RETURN_c; RETURN_5c: ext = RETURN_5c; RETURN_c: ext = ILE; RETURN_5c: ext = ILE; default: ext = ILE; case Combiatioal output assigmet assig C = (state == GOT_3c state == GOT_35c state == GOT_4c state == GOT_45c state == GOT_5c); assig N = (state == RETURN_5c); assig = (state == RETURN_2c state == RETURN_5c state == RETURN_c); module 2

21 Simulatio of Moore Ver State idle got5c got5c got2c got45c rt5 rt5 idle Output C 5 2

22 Codig Alterative: Two Blocks Next-state ad output logic combied ito a sigle always block (state or N or or ) begi C = ; = ; N = ; // defaults case (state) ILE: if () ext = GOT_25c; else if () ext = GOT_c; else if (N) ext = GOT_5c; else ext = ILE; GOT_5c: if () ext = GOT_3c; else if () ext = GOT_5c; else if (N) ext = GOT_c; else ext = GOT_5c; GOT_c: if () ext = GOT_35c; else if () ext = GOT_2c; else if (N) ext = GOT_5c; else ext = GOT_c; GOT_5c: if () ext = GOT_4c; else if () ext = GOT_25c; else if (N) ext = GOT_2c; else ext = GOT_5c; GOT_2c: if () ext = GOT_45c; else if () ext = GOT_3c; else if (N) ext = GOT_25c; else ext = GOT_2c; GOT_25c: if () ext = GOT_5c; else if () ext = GOT_35c; else if (N) ext = GOT_3c; else ext = GOT_25c; GOT_3c: begi C = ; ext = ILE; GOT_35c: begi C = ; ext = RETURN_5c; GOT_4c: begi C = ; ext = RETURN_c; GOT_45c: begi C = ; ext = RETURN_5c; GOT_5c: begi C = ; ext = RETURN_2c; RETURN_2c: begi = ; ext = RETURN_c; RETURN_5c: begi = ; ext = RETURN_5c; RETURN_c: begi = ; ext = ILE; RETURN_5c: begi N = ; ext = ILE; default: ext = ILE; case 22

23 FSM Output Glitchig FSM state bits may ot trasitio at precisely the same time Combiatioal logic for outputs may cotai hazards Result: your FSM outputs may glitch! durig this state trasitio......the state registers may trastio like this......causig the C output to glitch like this! gotc gotc = got3c glitch got2c got2c assig C = (state == GOT_3c state == GOT_35c state == GOT_4c state == GOT_45c state == GOT_5c); If the soda dispeser is glitch-sesitive, your customers ca get a 2-cet soda! 23

24 Registered FSM Outputs are Glitch-Free Output Comb. Output Registers registered outputs iputs Next- State Comb. ext state State Registers preset state S Move output geeratio ito the sequetial always block Calculate outputs based o ext state reg C,N,; // Sequetial always block for state assigmet (posedge clk or egedge reset) begi if (!reset) state <= ILE; else if (clk) state <= ext; C <= (ext == GOT_3c ext == GOT_35c ext == GOT_4c ext == GOT_45c ext == GOT_5c); N <= (ext == RETURN_5c); <= (ext == RETURN_2c ext == RETURN_5c ext == RETURN_c); 24

25 Mealy Ver (covered i Recitatio) = N= idle got5c A Mealy machie ca elimiate states devoted solely to holdig a output value. N= = gotc = = = = = N= N= N= got5c got2c got25c N= got3c C= got35c C= got4c C= got45c C= got5c C= = = = = rt5 N= rt = rt5 = rt2 = = = C= = = = C= = N= C= N= idle got5c N= gotc N= got5c N= got2c N= got25c = = C= = C= = C= = C= N= = C= rt5 rt rt5 rt2 = = = 25

26 Verilog for Mealy FSM module mealyver (N,,, C, N,, clk, reset, state); iput N,,, clk, reset; output C, N, ; reg C, N, ; output [3:] state; reg [3:] state, ext; parameter ILE = ; parameter GOT_5c = ; parameter GOT_c = 2; parameter GOT_5c = 3; parameter GOT_2c = 4; parameter GOT_25c = 5; parameter RETURN_2c = 6; parameter RETURN_5c = 7; parameter RETURN_c = 8; parameter RETURN_5c = 9; // Sequetial always block for state assigmet (posedge clk or egedge reset) if (!reset) state <= ILE; else state <= ext; 26

27 Verilog for Mealy FSM (state or N or or ) begi C = ; N = ; = ; // defaults case (state) ILE: if () ext = GOT_25c; else if () ext = GOT_c; else if (N) ext = GOT_5c; else ext = ILE; GOT_5c: if () begi C = ; ext = ILE; else if () ext = GOT_5c; else if (N) ext = GOT_c; else ext = GOT_5c; GOT_c: if () begi C = ; ext = RETURN_5c; else if () ext = GOT_2c; else if (N) ext = GOT_5c; else ext = GOT_c; GOT_5c: if () begi C = ; ext = RETURN_c; else if () ext = GOT_25c; else if (N) ext = GOT_2c; else ext = GOT_5c; GOT_2c: if () begi C = ; ext = RETURN_5c; else if () begi C = ; ext = ILE; else if (N) ext = GOT_25c; else ext = GOT_2c; For state GOT_5c, output C is oly asserted if = GOT_25c: if () begi C = ; ext = RETURN_2c; else if () begi C = ; ext = RETURN_5c; else if (N) begi C = ; ext = ILE; else ext = GOT_25c; RETURN_2c: begi = ; ext = RETURN_c; RETURN_5c: begi = ; ext = RETURN_5c; RETURN_c: begi = ; ext = ILE; RETURN_5c: begi N = ; ext = ILE; default: ext = ILE; case module 27

28 Simulatio of Mealy Ver State idle got5c got5c got2c rt5 rt5 idle Output C 5 (ote: outputs should be registered) 28

29 elay Estimatio : Simple RC Networks V V i 5% Vi Vout t CL V out t phl t plh 9% V V 5% % t R o (a) Low-to-high (b) High-to-low review t f R t r vout V out V out vi C C L C L R o t p = l (2) τ =.69 RC 29

30 Clocks are Not Perfect: Clock Skew CLout I Combiatioal Clk Wire delay Clk δ> T > T cq + T logic + T su - δ T cq,cd + T logic,cd > T hold + δ 3

31 Positive ad Negative Skew I R Combiatioal R2 Combiatioal R3 δ T + δ T 3 t delay t 2 (a) Positive skew delay t δ + t h 4 Lauchig edge arrives before the receivig edge I R Combiatioal R2 Combiatioal R3 T + δ T 3 t t 2 t 3 delay (b) Negative skew delay 2 2 δ 4 Receivig edge arrives before the lauchig edge 3

32 Clocks are Not Perfect: Clock Jitter 2 T t jitter -t jitter 6 I REGS t c-q, t c-q, cd t su, t hold t jitter Combiatioal t logic t logic, cd T 2t jitter > t c q + t logic +t su or T> t c q + t log ic + t su + 2t jitter 32

33 Summary Sychroize all asychroous iputs Use two back to back registers Two types of Fiite State Machies itroduced Moore outputs are a fuctio of curret state Mealy outputs a fuctio of curret state ad iput A stadard template ca be used for codig FSMs Register outputs of combiatioal logic for critical cotrol sigals Clock skew ad jitter are importat cosideratios 33

Module Instantiation. Finite State Machines. Two Types of FSMs. Finite State Machines. Given submodule mux32two: Instantiation of mux32two

Module Instantiation. Finite State Machines. Two Types of FSMs. Finite State Machines. Given submodule mux32two: Instantiation of mux32two Give submodule mux32two: 2-to- MUX module mux32two (iput [3:] i,i, iput sel, output [3:] out); Module Istatiatio Fiite Machies esig methodology for sequetial logic -- idetify distict s -- create trasitio