EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 13 Control and Sequencing: Hardwired and Microprogrammed Control

Transcription

1 EE 459/500 HDL Based Digital Desig with Programmable Logic Lecture 13 Cotrol ad Sequecig: Hardwired ad Microprogrammed Cotrol Refereces: Chapter s 4,5 from textbook Chapter 7 of M.M. Mao ad C.R. Kime, Logic ad Computer Desig Fudametals, Pearso Pretice-Hall, Overview Cotrol ad Sequecig Algorithmic State Machie (ASM) Chart of Multiplier Hardwired cotrol Microprogrammed cotrol 2 1

2 Multiplier Example Example: (101 x 011) Partial products are: 101 x 0, 101 x 1, ad 101 x x Example (1 0 1) x (0 1 1) agai Reorgaizig to follow hardware algorithm: x Multiplicad (B) Multiplier (Q) Clear C A (Carry ad register A) Multiplier 0 = 1 => Add B Additio Shift Right (Zero-fill C) Multiplier 1 = 1 => Add B Additio Shift Right Multiplier 2 = 0 => No Add, Shift Right 2

3 Multiplier Example: Block Diagram log 2-1 Couter P IN Multiplicad Register B G (Go) Zero detect C out Parallel adder Cotrol uit 4 Z Q o Multiplier 0 C Shift register A Shift register Q Cotrol sigals Product OUT Multiplier Example: Operatio 1. The multiplicad is loaded ito register B. 2. The multiplier is loaded ito register Q. 3. Whe G becomes 1, register C A is iitialized to Dow Couter P is iitialized to 1 ( = umber of bits i multiplier) 5. The partial products are formed i register C A Q. 6. Each multiplier (Q) bit, begiig with the LSB, is processed (if bit is 1, B is added to partial product of A; if bit is 0, do othig) 7. C A Q is shifted right usig the shift register Partial product bits fill vacat locatios i Q as multiplier is shifted out If overflow durig additio, the outgoig carry is recovered from C durig the right shift 8. Steps 6 ad 7 are repeated util P = 0 as detected by Zero detect. 3

4 Multiplier Example: ASM Chart IDLE MUL0 0 1 G C 0, A 0 P Q 0 A A + B, C C out MUL1 C 0, C A Q sr C A Q, P P Z 7 Multiplier Example: ASM Chart (Cotd.) Three states are ecessary to implemet multiplier IDLE state: Iput G is used as the coditio for startig the multiplicatio C, A, ad P are iitialized MUL0 state: coditioal additio is performed based o the value of Q 0. MUL1 state: Right shift is performed to capture the partial product ad positio the ext bit of the multiplier i Q 0 Dow couter P = P - 1 P=0 is used to sese completio or cotiuatio of the multiplicatio. 4

5 Cotrol ad sequecig The ASM chart provides iformatio about Cotrol of the microoperatios (cotrol word) Sequecig of these operatios The desig ca be split up i two parts: Cotrol sigals Sequecig 9 Cotrol sigals for multiplier Iitialize Shift_dec - 1 Couter P IN Multiplicad Register B Load_B log 2 G (Go) Zero detect C out Parallel adder Cotrol uit Z Q o Load Multiplier 0 C Shift register A Shift register Q Load_Q 4 Cotrol sigals Clear_C Iitialize Shift_dec Product OUT 10 5

6 Multiplier Example: Cotrol Sigal Table Cotrol Sigals for Biary Multiplier Block diagram module Microoperatio Cotrol sigal ame Cotrol sigal expressio Register A : A 0 I itia liz e IDLE G A A + B Load MUL0 Q 0 C A Q sr C A Q Shift_dec M UL1 Register B : B IN Load_B LO ADB F lip-f lop C : C 0 C lea r _C IDLE G + MUL1 C C ou t Load Register Q : Q IN Load_Q LO ADQ C A Q sr C A Q Shift_dec Cou ter P : P 1 I itia liz e P P 1 Shift_dec 11 Multiplier Example: Cotrol Sigal Table (Cotd.) Sigals are defied o a register basis LOAD_Q ad LOAD_B: exteral sigals cotrolled from the system usig the multiplier ad will ot be cosidered a part of this desig Some cotrol sigals are reused for differet registers. Four cotrol sigals are the outputs of the cotrol uit: iitialize, load, shift_dec, clear_c 12 6

7 Multiplier Example Sequecig part of ASM With the outputs represeted by the table, they ca be removed from the ASM makig the ASM to represet oly the sequecig (ext state) behavior Simplified ASM chart. Similar to a state diagram/graph but without outputs specified. IDLE 00 0 G 1 MUL0 01 MUL Z 1 13 Overview Cotrol ad Sequecig Algorithmic State Machie (ASM) Chart of Multiplier Hardwired cotrol Microprogrammed cotrol 14 7

8 Cotrol Hardwired Cotrol Implemeted usig gates ad flip-flops Faster, less flexible, limited complexity Microprogram Cotrol Cotrol Store Memory storig cotrol sigals ad ext state ifo Cotroller sequeces through memory Slower, more flexible, greater complexity 15 Hardwired cotrol Cotrol Desig Methods (1) Sequetial circuit techiques; studied earlier i this course Procedure specializatios that use a sigle sigal to represet each state (2) Sequece Register ad Decoder Sequece register with ecoded states, e.g., 00, 01, 10, 11. Decoder outputs produce state sigals, e.g., 0001, 0010, 0100, (3) Oe Flip-Flop per State Flip-flop outputs as state sigals, e. g., 0001, 0010, 0100,

9 (2) Sequecer (sequece register) ad Decoder Use a register to represet the states ad a decoder to geerate a output sigal correspodig to each state Use the State Table to fid the iput logic Iput Logic 17 Multiplier Example: Sequecer ad Decoder Desig - Specificatio Defie: States: IDLE, MUL0, MUL1 Iput Sigals: G, Z, Q 0 (Q 0 affects outputs, ot ext state) Output Sigals: Iitialize, Load, Shift_Dec, Clear_C State Trasitio Diagram (Use Sequecig ASM) Output Fuctio: Use Cotrol Sigal Table Decide o type of flip-flops to use Fid: State Assigmets Use two state bits to ecode the three states IDLE, MUL0, ad MUL1. State M1 M0 IDLE 0 0 MUL0 0 1 MUL1 1 0 Uused

10 Multiplier Example: Sequecer ad Decoder Desig - Formulatio Assumig that state variables M1 ad M0 are decoded ito states, the ext state part of the State Table is: Curret State Iput G Z Next State M1 M0 IDLE IDLE IDLE IDLE MUL MUL MUL MUL Curret State Iput G Z Next State M1 M0 MUL MUL MUL MUL Uused 0 0 d d Uused 0 1 d d Uused 1 0 d d Uused 1 1 d d 19 State Table with Decoder Outputs 20 10

11 Multiplier Example: Sequecer ad Decoder Desig - Equatios Derivatio/Optimizatio Fidig the equatios for M1 ad M0 usig decoded states: M1 = MUL0 M0 = IDLE G + MUL1 Z The output equatios usig the decoded states: Iitialize = IDLE G Load = MUL0 Q 0 Clear_C = IDLE G + MUL1 Shift_dec = MUL1 Doig multiple level optimizatio, extract IDLE G: START = IDLE G M1 = MUL0 M0 = START + MUL1 Z Iitialize = START Load = MUL0 Q 0 Clear_C = START + MUL1 Shift_dec = MUL1 The resultig circuit usig flip-flops, a decoder, ad the above equatios is give o the ext slide. 21 Multiplier Example: Sequecer ad Decoder Desig - Implemetatio G START D M 0 Iitialize Clear_C Z C DECODER A A1 3 IDLE MUL0 MUL1 Shift_dec M 1 D C Q 0 Load 22 11

12 --Biary multiplier with =4 library ieee; use ieee.std_logic_usiged.all; etity biary_multiplier is port(clk, RESET, G, LOADB, LOADQ : i std_logic; MULT_IN : i std_logic_vector (3 dowto 0); MULT_OUT : out std_logic_vector (7 dowto 0)); ed biary_multiplier; architecture behavior_4 of biary_multiplier is type state_type is (IDLE, MUL0, MUL1); variable P :=3; sigal state, ext_state : state_type; sigal A, B, Q : std_logic_vector(3 dowto 0); sigal C, Z : std_logic; begi Z <= P(1) NOR P(0); MULT_OUT <= A & Q; state_register : process (CLK, RESET) begi if (RESET = '1') the state <= IDLE; elsif (CLK'evet ad CLK='1') the state <= ext_state; edif; ed process; ext_state_fuc : process (G, Z, state) begi case state is whe IDLE => if G='1' the ext_state <= MUL0; else ext_state <= IDLE; ed if; whe MUL0 => ext_state <= MUL1; whe MUL1 => if Z='1' the ext_state <= IDLE; else ext_state <= MUL0; ed if; ed case; ed process; VHDL code: behavioral 3 processes datapath_fuc : process (CLK) variable CA : std_logic_vector (4 dowto 0); begi if (CLK'evet ad CLK='1') the if LOADB='1' the B <= MULT_IN; ed if; if LOADQ = '1' the Q <= MULT_IN; ed if; case state is whe IDLE => if G = '1' the C <= '0'; A <= "0000"; P <= "11"; ed if; whe MUL0 => if Q(0) ='1' the CA := ('0' & A) + ('0' & B); else CA := C & A; ed if; C <= CA(4); A <= CA(3 dowto 0); whe MUL1 => C <= '0'; A <= C & A(3 dowto 1); Q <= A(0) & Q(3 dowto 1); P <= P - "01"; ed case; ed if; ed process; ed behavior_4; 23 VHDL code: structural Homework assigmet #5: Write VHDL descriptio of structural architecture similar to the structural descriptio of the architecture from Example 2, Implemetatio 2 of Lab #4. Create a testbech ad simulate i Aldec-HDL. Report should cotai: title, ame, brief descriptio, VHDL code (with ice idetatio ad useful commets throughout the code), simulatio waveforms (black o white ad horizotal). Report should be a sigle PDF file amed hw5_yourfirstname_yourlastname.pdf 24 12

13 (3) Oe Flip-Flop per State This method uses oe flip-flop per state ad a simple set of trasformatio rules to implemet the circuit. The desig starts with the ASM chart, ad replaces 1. State Boxes with flip-flops, 2. Scalar Decisio Boxes with a demultiplexer with 2 outputs, 3. Vector Decisio Boxes with a (partial) demultiplexer, 4. Juctios with a OR gate, ad 5. Coditioal Outputs with AND gates. More flip-flops eeded tha i previous method 25 State box ad Scalar decisio box trasformatios 13

14 Vector decisio box trasformatio Each Decisio box trasforms to a Demultiplexer Etry poit is Eable iputs The Coditios are the Select iputs Demultiplexer Outputs are the Exit poits (Biary Vector Values) (Vector of Iput Coditios) X1, X0 (Biary Vector Values) 10 DEMUX Etry EN D0 Exit 0 X1 A1 D1 Exit 1 X0 A0 D2 D3 Exit2 Exit 3 Juctio trasformatio, Coditioal output box trasformatio 14

15 Logic Diagram Overview Cotrol ad Sequecig Algorithmic State Machie (ASM) Chart of Multiplier Hardwired cotrol Microprogrammed cotrol 15

16 Datapath + Cotrol uit/path Datapath - performs data trasfer ad processig operatios Cotrol uit/path - determies the eablig ad sequecig of the operatios Status sigals Describe properties of the state of the datapath Cotrol iputs Cotrol uit Cotrol sigals Datapath Data outputs Cotrol outputs Data iputs Datapath + Cotrol uit/path Datapath: Registers MUXes, ALUs, Shifters, Combiatioal Circuits ad Buses Implemets microoperatios (uder cotrol of the cotrol uit) Cotrol uit: Selects the microoperatio Determies the sequece (based o status ad iput sigals) Desig: State diagram or ASM Microoperatios Sequece 16

17 Multiplier Example Microprogrammed Cotrol Is a cotrol uit whose cotrol words are stored i memory, called cotrol memory. A cotrol word cotais a microistructio that specifies oe or more microoperatios. A sequece of microistructios is called a microprogram. A microprogram is stored i ROM (thus fixed) or i RAM (called writable cotrol memory). 17

18 Cotrol Uit Orgaizatio Microprogrammed Cotrol The Cotrol Data Register (CDR) is optioal: Allows higher clock frequecies (pipeliig) Makes the sequecig more complicated for decisios based o status bits If the CDR is omitted: The oly register i the cotrol uit is the Cotrol Address Register (CAR) The memory ad ext-address geerator are combiatioal Thus the state of the cotrol uit is give by the cotets of the CAR New cotrol data will appear at the output of the memory as log as the address is applied 18

19 Microprogrammed Cotrol The ext address (determiig the ext istructio of the ew state) is fuctio of the ext-address bits ad the STATUS sigals/bits. The way we desiged the cotrol uit, the status bits ca oly affect the ext address (thus ext state). [ote: status bits do ot cotrol the datapath directly] Thus status bits caot directly affect the output or cause a register trasfer operatio (except by affectig the address). This meas that the sequetial circuit of the cotrol uit must be a Moore type. ASM of the Cotrol Uit Moore type circuit: No coditioal output boxes allowed Replace the coditioal output boxes by states Additioal states are required for the same hardware algorithm Also, oly oe decisio box betwee states preferred (for simple ext address geeratio) 19

20 ASM of the Cotrol Uit 39 ASM of the Cotrol Uit Two additioal states: INIT, ADD Total of 5 states eeded 20

21 Desig of the Cotrol Uit To desig the (micro)sequecer for the multiplier ad the microprogram we eed to determie: The bits i the cotrol word The size of the Cotrol memory (ROM) The size of the Cotrol Address Register (CAR) Next-address geerator structure Cotrol word Sequecer Cotrol Sigals ad Datapath Use the same Datapath: - 1 Couter P IN Multiplicad Register B Load_B log 2 We eed four cotrol sigals: Iitialize Load Clear_C Shift_Dec Status bits: Qo, Z Zero detect Z Q o C out Parallel adder Multiplier 0 C Shift register A Shift register Q Clear_C Iitialize Shift_dec Load Product OUT Load_Q 42 21

22 Cotrol Sigals ad Register Trasfers From the datapath ad ASM oe fids the register trasfers iitiated by the cotrol sigals. From the ASM oe fids the states i which the sigals are active 43 Cotrol Sigals, Cotrol Word Format Four cotrol sigals eeded. We ca use these sigals as is or ecode them to reduce the umber of bits eeded i the cotrol word. If we do ot ecode these: 4 bits eeded Iitialize 0001 Load 0010 ClearC 0100 Shift/Dec

23 Sequecer The sequecig is determied by the ASM chart First, determie the sequecig requiremets: IDLE: ext state fuctio of G MUL0: ext state fuctio of Qo MUL1: ext state fuctio of Z We eed a pair of addresses to direct to the ext state depedig o the values of the status or iput sigals SEL determies which ext address to use 45 Cotrol Sequeces for the micro operatios based o decisio boxes i the ASM chart: 46 23

24 SEL Field defiitio ad Code i the Cotrol Word 47 Desig of Cotrol Uit ROM size: Word legth: 12 bits (cotrol word) Size: 5 storage locatio, oe for each state Address bits: 3 bits to address 5 locatios CAR is 3 bits wide The address loaded i the CAR: Comes from the ext-address ifo i the microistructio: NXTADD0 or NXTADD1 24

25 Microprogrammed Cotrol Uit 49 Register Trasfer Descriptio of the Microprogram Each memory locatio cotais a microistructio, to be executed i the correspodig state. The register trasfer statemets are: 25

26 Symbolic Microprogram The above Register Trasfer Operatio ca be traslated ito a symbolic microprogram (cotrol words): Example: address IDLE: G: CAR INIT, G : CAR IDLE Ca be writte as: 51 Symbolic Microprogram 52 26

27 Biary Microprogram Similar for the other istructios: 53 VHDL code Homework assigmet #6: Write VHDL structural descriptio of this multiplier (slide #49) usig the microprogrammed approach for the cotrol uit. Use a ROM as studied i Lab #5. Create a testbech ad simulate i Aldec-HDL. Report should cotai: title, ame, brief descriptio, VHDL code (with ice idetatio ad useful commets throughout the code), simulatio waveforms (black o white ad horizotal). Report should be a sigle PDF file amed hw6_yourfirstname_yourlastname.pdf 54 27

28 Summary Iteractio betwee datapaths ad cotrol uits Two types of cotrol uits: No-programmed Programmed Two implemetatio approaches for Hardwired Cotrol (o-programmed): Sequece Register ad Decoder Oe Flip-Flop per state Use of ASM to specify cotrol fuctios: Microoperatios Sequece of operatios Microprogrammed cotrol is a more structured approach for complex systems 55 Appedix A: Speedig Up the Multiplier I processig each bit of the multiplier, the circuit visits states MUL0 ad MUL1 i sequece. By redesigig the multiplier, is it possible to visit oly a sigle state per bit processed? 56 28

29 Speedig Up Multiply (Cotd.) The operatios i MUL0 ad MUL1: I MUL0, a coditioal add of B I MUL1, a right shift of C A Q i a shift register, the decremetig of P, ad a test for P = 0 (o the old value of P) Ay solutio that uses oe state must combie all of the operatios listed ito oe state The operatios ivolvig P are already doe i a sigle state, so ot a problem. The right shift, however, depeds o the result of the coditioal additio. So these two operatios must be combied! 57 Speedig Up Multiply (Cotd.) By replacig the shift register with a combiatioal shifter ad combiig the adder ad shifter, the states ca be merged. IDLE 0 1 G The C-bit is o loger eeded. I this case, Z ad Q 0 have bee made ito a vector. A Q sr C out (A + 0) Q MUL A 0 P 1 P P 1 Z Q 0 A Q sr C out (A + 0) Q A Q sr C out (A + B) Q A Q sr C out (A+ B) Q 58 29