EE260: Digital Design, Spring /16/18. n Example: m 0 (=x 1 x 2 ) is adjacent to m 1 (=x 1 x 2 ) and m 2 (=x 1 x 2 ) but NOT m 3 (=x 1 x 2 )

Transcription

1 EE26: Digital Desig, Sprig 28 3/6/8 EE 26: Itroductio to Digital Desig Combiatioal Datapath Yao Zheg Departmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa Combiatioal Logic Blocks Multiplexer Ecoders/Decoders Priority Ecoders Three-State Buffers Parity Fuctios Comparators Adders/Subtractors Multipliers/Dividers Shifters Memory/Cache Overview Caoical ad Stadard Forms Karaugh Maps We eed to cosider formal techiques for the simplificatio of Boolea fuctios. Miterms ad Maxterms Sum-of-Miterms ad Product-of-Maxterms Product ad Sum terms Sum-of-Products (SOP) ad Product-of-Sums (POS) Karaugh maps (K-maps) are graphical represetatios of boolea fuctios. Oe map cell correspods to a row i the truth table. Also, oe map cell correspods to a miterm or a maxterm i the boolea expressio Multiple-cell areas of the map correspod to stadard terms. 3 4 x x 2 Two-Variable Map m 2 3 m 2 m m 3 OR x 2 x 2 NOTE: orderig of variables is IMPORTANT for f(x,x2), x is the row, x2 is the colum. Cell represets x x2 ; Cell represets x x2; etc. If a miterm is preset i the fuctio, the a is placed i the correspodig cell. m 3 m m 2 m 3 5 Two-Variable Map (cot.) Ay two adjacet cells i the map differ by ONLY oe variable, which appears complemeted i oe cell ad ucomplemeted i the other. Example: m (=x x 2 ) is adjacet to m (=x x 2 ) ad m 2 (=x x 2 ) but NOT m 3 (=x x 2 ) 6 Chapter 6-8: Combiatioal Datapath

2 EE26: Digital Desig, Sprig 28 3/6/8 Simplificatio Eter miterms of the Boolea fuctio ito the map, the group terms Example: f(a,b,c) = a c + abc + bc Result: f(a,b,c) = a c + b a bc 7 Elimiatig static hazards Key idea: Glitches happe whe a chagig iput spas separate K-map ecirclemets Example: to chage ca cause a static- glitch AB A CD C B D Combiatioal Logic Blocks With K map, you ca build ay combiatioal fuctios you wat, but ot everythig should be build from K map Miimum SOP/POS is ot always globally optimum Some fuctios have special structures to be take advatage of Some fuctios are so frequetly used they have become covetios Major examples Multiplexer Ecoders/decoders Arithmetic: adders, subtractors, multipliers, dividers, etc. Logic: shifters Memory: ROM, RAM Multiplexer Selects biary iformatio from oe of may iput lies ad directs it to a sigle output lie. Also kow as the selector circuit, Selectio is cotrolled by a particular set of iputs lies whose # depeds o the # of the data iput lies. For a 2 -to- multiplexer, there are 2 data iput lies ad selectio lies whose bit combiatio determies which iput is selected. 2-to--Lie Multiplexer Sice 2 = 2, = The sigle selectio variable S has two values: S = selects iput I S = selects iput I The equatio: Y = S I + SI The circuit: S Decoder I I Eablig Circuits Y Implemetig Boolea fuctios with Multiplexers Ay Boolea fuctio of variables ca be implemeted usig a 2 - -to- multiplexer. A MUX is basically a decoder with outputs ORed together, hece this is t surprisig. The SELECT sigals geerate the miterms of the fuctio. The data iputs idetify which miterms are to be combied with a OR. Chapter 6-8: Combiatioal Datapath 2

3 EE26: Digital Desig, Sprig 28 3/6/8 Example F(X,Y,Z) = X Y Z + X YZ + XYZ + XYZ = Σm(,2,6,7) There are =3 iputs, thus we eed a 2 2 -to- MUX The first - (=2) iputs serve as the selectio lies Decoders A combiatioal circuit that coverts biary iformatio from coded iputs to a maximum 2 coded outputs à -to- 2 decoder -to-m decoder, m 2 Examples: BCD-to-7-segmet decoder, where =4 ad m= -2 Decoder Implemetig Boolea fuctios usig decoders Ay combiatioal circuit ca be costructed usig decoders ad OR gates! Why? Here is a example: Implemet a full adder circuit with a decoder ad two OR gates. Recall full adder equatios, ad let X, Y, ad Z be the iputs: S(X,Y,Z) = X+Y+Z = Sm(,2,4,7) C (X,Y,Z) = Sm(3, 5, 6, 7). Sice there are 3 iputs ad a total of 8 miterms, we eed a 3-to-8 decoder. Implemetig a Biary Adder Usig a Decoder S(X,Y,Z) = SUM m(,2,4,7) C(X,Y,Z) = SUM m(3,5,6,7) Ecoders A ecoder is a digital circuit that performs the iverse operatio of a decoder. A ecoder has 2 iput lies ad output lies. The output lies geerate the biary equivalet to the iput lie whose value is. Chapter 6-8: Combiatioal Datapath 3

4 EE26: Digital Desig, Sprig 28 3/6/8 Ecoder Example Example: 8-to-3 biary ecoder (octal-to-biary) A = D + D 3 + D 5 + D 7 A = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 Ecoder Desig Issues There are two ambiguities associated with the desig of a simple ecoder:. Oly oe iput ca be active at ay give time. If two iputs are active simultaeously, the output produces a udefied combiatio (for example, if D 3 ad D 6 are simultaeously, the output of the ecoder will be. 2. A output with all 's ca be geerated whe all the iputs are 's,or whe D is equal to. Priority Ecoders Solves the ambiguities metioed above. Multiple asserted iputs are allowed; oe has priority over all others. Separate idicatio of o asserted iputs. Example: 4-to-2 Priority Ecoder Truth Table Example: 4-to-2 Priority Ecoder K-Maps Buffers The umber of circuit iputs that ca be drive by a sigle output is limited If a circuit output must drive may iputs, we use buffers to icrease the drivig capability Buffers does ot perform ay logic fuctio, i.e. its logic equatio is F=C. It oly icreases the drivig capability Chapter 6-8: Combiatioal Datapath 4

5 EE26: Digital Desig, Sprig 28 3/6/8 Three-state buffers Logic values for buses sigals Output = LOW, HIGH, or Hi-Z. lca tie multiple outputs together, if at most oe at a time is drive. Circuit with tri-state buffers S S2 X Z X X X X X X X X X Z X Z Table : Logic values for bus sigals ad the resultig value whe they are coected together Exclusive-OR (XOR) Fuctio XOR (also Å) : the ot-equal fuctio XOR(X,Y) = X Å Y = X Y + XY Idetities: X Å = X X Å = X X Å X = X Å X = Properties: X Å Y = Y Å X (X Å Y) Å W = X Å ( Y Å W) Parity Fuctios Odd Parity Circuit : The output is if odd umber of iputs are Eve Parity Circuit : The output is if eve umber of iputs are Example : 4-bit Parity Circuit I I I2 I3 Daisy-Chai Structure EVEN ODD Iput : Odd Parity output : Eve Parity output : I I I2 I3 Tree structure EVEN ODD 28 Parity-Checkig Applicatio: memory Comparators Compares Two biary words ad idicate if they are equal A B Comparator A=B? Magitude Comparators : A B Comparator A=B A>B A<B 29 3 Chapter 6-8: Combiatioal Datapath 5

6 EE26: Digital Desig, Sprig 28 3/6/8 Equality Comparators Iterative Comparator -bit comparator l4-bit comparator EQ_L 3 32 Performs -bit additio. Iputs: A, B Half Adder Outputs: S, C Idex idicates sigificace, is for LSB ad is for the ext higher sigificat bit. Boolea equatios: S = A B +A B = A Å B C = A B Truth Table A B S C Full Adder Full adder (for higher-order bit additio) Combiatioal circuit that performs the additios of 3 bits (two bits ad a carry-i bit) C i+ B i bit full adder C i S i Full Adder (cot.) -bit Combiatioal Adders The K-maps for C i+ : S i : B i C i B i C i B i C i S i C i+ Perform parallel multi-bit additio Ripple Carry Adder Simple desig Time cosumig. Why? (you ll see i a bit!) Carry Lookahead Adder More complex tha ripple-carry adder Reduces circuit delay Chapter 6-8: Combiatioal Datapath 6

7 EE26: Digital Desig, Sprig 28 3/6/8 -bit Ripple Carry Adder Costructed usig -bit full adder blocks i parallel. Cascade the full adders so that the carry out from oe becomes the carry i to the ext higher bit positio. Carry Lookahead Adder From a FA, separate betwee carry geeratio (a ew carry sigal is geerated, i.e. C out =) ad carry propagatio (a existig C i is propagated to C out ) Geerate: G i = B i : if, C i+ = Propagate: P i = Å B i : if true, C i+ = C i Full Adder (FA) Partial Full Adder (PFA) B i B i S i C i+ C i S i G i P i Ci 4-bit Biary Adder/Subtractor Multiplicatio XOR gates act as programmable iverters Flashback to 3 rd grade Multiplier Multiplicad Partial products Fial sum Base : 8 x 9 = 72 PP: = 72 How wide is the result? log( x m) = log() + log(m) 32b x 32b = 64b result x Array Multiplier x Addig all partial products simultaeously usig a array of basic cells S i C i B j Full Adder C out S out,b j Multiplier Multiplicad 32 bits 32-bit ALU Shift right Product Write 64 bits x Cotrol test Chapter 6-8: Combiatioal Datapath 7

8 EE26: Digital Desig, Sprig 28 3/6/8 Booth s Ecodig Search for a ru of bits i the multiplier E.g. has a ru of 2 bits i the middle Multiplyig by (6 i decimal) is equivalet to multiplyig by 8 ad subtractig twice, sice 6 x m = (8 2) x m = 8m 2m Hece, iterate right to left ad: Subtract multiplicad from product at first Add multiplicad to product after last Do t do either for bits i the middle Iteger Divisio Agai, back to 3 rd grade (74 8 = 9 rem 2) Quotiet Divisor Divided - - Remaider 32-bit ALU Divisor 32 bits Divider Shift right Remaider Shift left Write 64 bits Cotrol test Logical Operatios Bitwise AND, OR, XOR, NOR Implemet w/ 32 gates i parallel Shifts ad rotates rol => rotate left (MSB->LSB) ror => rotate right (LSB->MSB) sll -> shift left logical (->LSB) srl -> shift right logical (->LSB) sra -> shift right arithmetic (old MSB->ew MSB) Memory: ROM Memory: RAM Iput: a -bit address Output: data of width w stored at locatio ROM[addr] (2^ such locatios) Sice it is read-oly, the ROM s cotets have to be iitialized by a offlie process If you just read the memory, memory is combiatioal The same address always returs the same aswer It is equivalet to a -iput combiatioal fuctio, each address is a miterim Chapter 6-8: Combiatioal Datapath 8

9 EE26: Digital Desig, Sprig 28 3/6/8 4 9 Processor Memory Hierarchy Small Fast Memory (RF, SRAM) Big Slow Memory (DRAM) Capacity: Register << SRAM << DRAM Latecy: Register << SRAM << DRAM Badwidth: o-chip >> off-chip O a data access: if data is i fast memory -> low-latecy access to SRAM if data is ot i fast memory -> log-latecy access to DRAM Memory hierarchies oly work if the small, fast memory actually stores data that is reused by the processor Combiatioal Datapath All digital systems comprise Iput ad output Combiatioal stuff that computes a fuctio (has o memory) Sequetial stuff that remembers (upcomig) Chapter 6-8: Combiatioal Datapath 9