8.0 Resolving Multi-Signal Drivers

Transcription

1 Fileame= ch8_2 8.0 Resolvig Multi-Sigal Drivers 8.1 Buses B ACTL BCTL DBUS DBUS A DBUS Ope circle deotes a iput coectio Solid dot deotes a output coectio The ope circles at the bus iputs respreset switched coectios ACTL BCTL DBUS 0 0 impemetatio depedet ( o iput activated) 0 1 B 1 0 A 1 1 implemetatio depedet (both iputs activated) 8.2 Bus Implemetatio NMOS Bus Driver 1

2 VDD C C i out = out i DBUS ACTL BCTL A B ACTL BCTL DBUS 0 0 Floatig 0 1 B 1 0 A 1 1 Udefied (Avoid) 2

3 8.2.2 Tri-State Bus Driver DBUS ACTL BCTL A B VDD C C i*c i out = out i*c i ACTL BCTL DBUS 0 0 Udefied (Avoid) 0 1 A 1 0 B 1 1 Floatig Whe C=1 both out trasistors are tured off ad the output out is left floatig C=0 oe of the output trastor is eabled ad the other disabled, as selected by the iput data i, out <= i. There are situatios where bus cotrol iputs are geerated by devices operatig idepedetly ad asychroously. Iterrupt request (IRQ) lies are a commo example. Multiple drivers ca be eabled simultaeously durig ormal operatio, ad hece tri-state bus should ot be used. 3

4 8.2.3 Ope-Drai Bus Driver C i out = C i i*c out VDD R DBUS ACTL BCTL A B The driver is a NOR gate followed by a iverter with the pull-up resistor removed. A pull-up resistor is provided exterally to hold the bus at 1 whe o driver is pullig it low. Whe o driver is eabled, DBUS = 1. If multiple drivers are eabled, the the bus will be pulled low if ay eabled iputs is low, hece DBUS is the AND of the eabled iputs. ACTL BCTL DBUS 0 0 A ad B 0 1 A 1 0 B Ope-Collector Bus Driver 4

5 out C i out = C i i*c VDD R DBUS ACTL BCTL DBUS A B TTL versio of the ope-drai OR-gate is the ope-collector NAND-gate. It is formed from the basic TTL gate by removig the pull-up from the output. The DBUS is the OR of the eabled iputs. ACTL BCTL DBUS DBUS B B 1 0 A A 1 1 A ad B A + B 5

6 8.3 Resolvig Multi-Sigal Drivers Simulators origially used a two-state value system, represetig logic 1 ad logic 0. This is declared as type BIT: TYPE BIT IS ( 0, 1 ); For a sigle source system this is adequate. Whe two or more souces are drivig a sigal, if oe source is drivig a value of 1 ad the other drivig a 0, the result deped o the techologies used, it may be desig error i some ad ukow i others. With two-state system, this state ca ot be represeted. To represet coditios of ukow state ad floatig state, a miimum of four-value system is required. This uresolved 4 logic state system (Autologic II, old stadard) is declared as: TYPE qsim_state IS ( X, --Forcig Ukow 0, --Forcig 0 1, --Forcig 1 Z --High Impedace ); To use this stadard logic system, VHDL code must iclude the followig lies at the begiig. LIBRARY MGC_PORTABLE; USE MGC_PORTABLE.QSIM_LOGIC.ALL; USE MGC_PORTABLE.QSIM_RELATIONS.ALL; For more complex circuit simulatio, the simulator must be able to represet sigals that do ot swig to the power rails of 1 (VDD), ad 0 (GND) such as TTL logic level where H meas >=2.5 ad L <= 0.8V. The ew IEEE STANDARD LOGIC 1164 (Autologic II, curret stadard) is a 9 value system. The uresolved 9 logic state system is declared as follows: TYPE std_ulogic IS ( U, --Uiitialized X, --Forcig Ukow 0, --Forcig 0 1, --Forcig 1 Z, --High Impedace W, --Weak Ukow L, --Weak 0 H, --Weak Do t care ); To use this stadard logic system, VHDL code must iclude the followig lies at the begiig. LIBRARY IEEE, ARITHMETIC; USE IEEE.STD_LOGIC_1164.ALL; USE ARITHMETIC.STD_LOGIC_ARITH.ALL; Resolvig a Sigal Value Whe Drive by Multiple Assigmets Every sigal assigmet statemet assigs a projected waveform to a driver. It is possible (ad probable i hardware desigs) that your model cotais more tha oe sigal assigmet statemet (each with its ow driver) that attempts to assig differet values to the same sigal at the same time. Whe this happes, your 6

7 model must provide a resolutio fuctio that specifies how to resolve the assigmet. Each sigal that requires a resolutio fuctio makes referece to the appropriate fuctio i the sigal declaratio. Example: ENTITY mult_driver IS PORT(a,b,c,d:IN qsim_state;z:out qsim_state); END mult_driver; ARCHITECTURE wired_ad OF mult_driver IS FUNCTION adig(drivers:qsim_state_vector)return qsim_state IS VARIABLE temp:qsim_state:='1'; FOR i IN drivers'range LOOP END LOOP; RETURN temp; END adig; temp:=temp AND drivers(i); SIGNAL lie_ad: adig qsim_state; lie_ad <= a; lie_ad <= b; lie_ad <= c; lie_ad <= d; z<= lie_ad; END wired_ad; --see the AND table Qsim AND Table AND 0 1 X Z X X X 0 X X X Z 0 X X X Std_ulogic AND TABLE AND U X 0 1 Z W L H - U U U 0 U U U 0 U U X U X 0 X X X 0 X X U X 0 1 X X 0 1 X Z U X 0 X X X 0 X X W U X 0 X X X 0 X X L H U X 0 1 X X 0 1 X - U X 0 X X X 0 X X 7

8 If the bus is wired or type replace the fuctio to orig: FUNCTION orig(drivers:qsim_state_vector)return qsim_state IS VARIABLE temp:qsim_state:='0'; FOR i IN drivers'range LOOP END LOOP RETURN temp; END orig;; temp:=temp OR drivers(i); SIGNAL lie_or: orig qsim_state; --see the OR table Qsim OR Table OR 0 1 X Z X X X X 1 X X Z X 1 X X Std_ulogic OR Table OR U X 0 1 Z W L H - U U U U 1 U U U 1 U X U X X 1 X X X 1 X 0 U X 0 1 X X 0 1 X Z U X X 1 X X X 1 X W U X X 1 X X X 1 X L U X 0 1 X X 0 1 X H U X X 1 X X X 1 X If the bus is either wired_ad or wired_or, such as wirig several sigals ito a commo ode. A ew two operad fuctio called wire is defied: TYPE qsim_2d IS ARRAY(qsim_state,qsim_state) OF qsim_state FUNCTION wire (a,b:qsim_state) RETURN qsim_state IS CONSTANT wire_table:qsim_2d:=( (`0','X','X','0'), (`X','1','X','1'), (`X','X','X','X'), (`0','1','X','Z')); RETURN wire_table(a,b); END wire; Qsim WIRE Table WIRE 0 1 X Z 0 0 X X 0 1 X 1 X 1 X X X X X Z 0 1 X Z 8

9 Std_ulogic WIRE Table U X 0 1 Z W L H - U U U U U U U U U U X U X X X X X X X X 0 U X 0 X X 1 U X X X Z U X 0 1 Z W L H X W U X 0 1 W W W W X L U X 0 1 L W L W X H U X 0 1 H W W H X - U X X X X X X X X NOTE: this is the same as resolutio_table i IEEE package Iterpretatio of wire: 1. IF the two iputs are equal, the wire value will be the same as the iputs. 2. wire(a,'z')=a, wire(`z',b)=b: Value `Z' o either of the iputs is absorbed by a stroger value (`0','1', or`x'). 3. wire(a,b)=x,if a<>b ad a<>'z' ad b<>'z': coflictig o `Z' values o the iputs result i `X' value. FUNCTION wirig(drivers:qsim_state_vector) RETURN qsim_state IS VARIABLE temp: qsim_state:='z'; FOR i IN drivers'range LOOP temp:=wire(temp,drivers(i)); END LOOP; RETURN temp; END wirig; SIGNAL bus_wire:wirig qsim_state; The correspodig resolvig fuctio of wirig i the 9-state logic system is give below: FUNCTION resolved (s ; std_ulogic_vector) RETURN std_ulogic IS VARIABLE result : std_ulogic := Z ; --weakest state default --the test for a sigle driver is essetial otherwise the --loop would retur X for a sigle driver of - ad that --would coflict with the value of a sigle driver uresolved sigal. IF (s LENGTH = 1) THEN RETURN s(s LOW); ELSE FOR i IN s RANGE LOOP result := resolutio_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved; SUBTYPE std_logic IS resolved std_ulogic; TYPE std_logic_vector IS ARRAY (NATURAL RANGE <>) OF std_logic; 9

10 The above resolutio fuctio are best put i a desig package iorder that they be available to all the desig etities. I additio, subtypes ad types ca be declared to hadle lie or bus cotetio that will facilitate sigal declaratio that requires resolutio fuctio. PACKAGE desig_package IS FUNCTION adig(drivers:qsim_state_vector)return qsim_state; SUBTYPE aded_qsim_state IS adig qsim_state; -- for resolvig lie drivers TYPE aded_qsim_state_vector IS ARRAY(NATURAL RANGE<>) OF aded_qsim_state; -- for resolvig bus drivers FUNCTION orig(drivers:qsim_state_vector)return qsim_state; SUBTYPE ored_qsim_state IS orig qsim_state; TYPE ored_qsim_state_vector IS ARRAY(NATURAL RANGE<>) OF ored_qsim_state; FUNCTION wirig(drivers:qsim_state_vector)return qsim_state; SUBTYPE wired_qsim_state IS wirig qsim_state; TYPE wired_qsim_state_vector IS ARRAY(NATURAL RANGE<>) OF wired_qsim_state ; END desig_package; PACKAGE BODY desig_package IS FUNCTION adig(drivers:qsim_state_vector)return qsim_state IS VARIABLE temp:qsim_state:='1'; FOR i IN drivers'range LOOP temp:=temp AND drivers(i); END LOOP; RETURN temp; END adig; FUNCTION orig(drivers:qsim_state_vector)return qsim_state IS VARIABLE temp:qsim_state:='0'; FOR i IN drivers'range LOOP temp:=temp OR drivers(i); END LOOP RETURN temp; END orig; TYPE qsim_2d IS ARRAY(qsim_state,qsim_state) OF qsim_state FUNCTION wire (a,b:qsim_state) RETURN qsim_state IS CONSTANT wire_table:qsim_2d:=( (`0','X','X','0'), (`X','1','X','1'), (`X','X','X','X ), (`0','1','X','Z')); RETURN wire_table(a,b); END wire; FUNCTION wirig(drivers:qsim_state_vector) RETURN qsim_state IS VARIABLE temp: qsim_state:='z'; FOR i IN drivers'range LOOP temp:=wire(temp,drivers(i)); END LOOP; 10

11 RETURN temp; END wirig; END desig_package; Depedig o the type of bus, they are declared accordigly: SIGNAL bus_ad : aded_qsim_state --for wired_ad bus SIGNAL bus_or : ored_qsim_state --for wired_or bus SIGNAL bus_wire: wired_qsim_state --for wired bus WIRED_AND BUS - OPEN COLLECTOR GATES The fuctio of resolutio fuctios ad resolved sigals is very useful for modelig various bus forms. A bussig structure formed by coectig the outputs of ope collector gates is very commo. The VHDL descriptio of a ope collector two-iput NAND gate is give as follows: ENTITY ad2 IS GENERIC(tplh:TIME:=10 s;tphl:time:=15 s); PORT(x,y:IN qsim_state;z:out qsim_state); END ad2; ARCHITECTURE ope_collector OF ad2 IS z<='0' AFTER tphl WHEN (x AND y)='1' ELSE `Z AFTER tplh WHEN (x AND y)='0' ELSE `X' AFTER tphl; END ope_collector; The output of a ope_collector gate must be coected to a pull-up,resistor to the power supply, several such outputs ca be coected to a commo pull-up resistor. I geeral, the fuctio of a pull-up resistor is to produce a `1' if oe of its drivers is `0', ad to produce a `0' if at least oe driver is `0'. For qsim_state type this is idetical to type aded_qsim_state. Therefore, a lie or bus coected to a pull-up resistor to a power supply is declared or modeled as follows: SIGNAL pull_up: aded_qsim_state; Associatig this sigal with a output port of a ope collector gate is equivalet to coectig that output to a pull-up resistor i hardware VHDL Implemetatio of 7403 ENTITY s7403 IS PORT(a,b:IN qsim_state_vector(1 TO 4);c:OUT qsim_state_vector(1 TO 4)); END s7403; ARCHITECTURE struct OF s7403 IS COMPONENT ad2 PORT(a,b:IN qsim_state;c:out qsim_state); END COMPONENT; FOR ALL:ad2 USE ENTITY WORK.ad2(ope_collector); g1: :ad2 PORT MAP(a(1),b(1),c(1)); g2: :ad2 PORT MAP(a(2),b(2),c(2)); g3: :ad2 PORT MAP(a(3),b(3),c(3)); g4: :ad2 PORT MAP(a(4),b(4),c(4)); END struct; 11

12 X_NOR Implemetatio usig s7403 ENTITY xor IS PORT(x,y:IN qsim_state;z:out qsim_state); END xor; ARCHITECTURE struct OF xor IS COMPONENT s7403 PORT(a,b:IN qsim_state_vector(1 TO 4);c:OUT qsim_state_vector(1 TO 4)); END COMPONENT; FOR ALL s7403 USE ENTITY WORK.s7403(struct); SIGNAL r1, r2, r3:aded_qsim_state:='z'; U1:s7403(x,y,r1, x, --a(1), a(2), a(3), a(4) x,y,y,r2, --b(1), b(2), b(3), b(4) r1, r2, r3, r3); --c(1), c(2), c(3), c(4) END struct; NOTE: r1, r2 are wired_ad bus with oe driver. r3 is a wired_ad bus with two drivers. 12

13 +5V x y g1 a(1) c(1) b(1) r1 x y g3 a(3) c(3) b(3) x y +5V r3 z =( x y ) ( x y ) = x y + x y a(2) c(2) b(2) g2 r2 x y a(4) c(4) b(4) g4 x y +5V WIRED BUS - MOS Multiplexer ENTITY mux_8_1 IS PORT(i,s :IN qsim_state_vector(7 DOWNTO 0); out:out qsim_state); END mux_8_1; ARCHITECTURE mult_guard OF mux_8_1 IS SIGNAL temp : wired_qsim_state BUS; b7: BLOCK(s(7)='1') temp<=guarded i(7);end BLOCK b6: BLOCK(s(6)='1') temp<=guarded i(6);end BLOCK b5: BLOCK(s(5)='1') temp<=guarded i(5);end BLOCK b4: BLOCK(s(4)='1') temp<=guarded i(4);end BLOCK b3: BLOCK(s(3)='1') temp<=guarded i(3);end BLOCK b2: BLOCK(s(2)='1') temp<=guarded i(2);end BLOCK b1: BLOCK(s(1)='1') temp<=guarded i(1);end BLOCK b0: BLOCK(s(0)='1') temp<=guarded i(0);end BLOCK out <= temp; END mult_guard; A iterestig situatio arises whe all the drivers are discoected from it, ad that is all eight implied GUARD sigals are FALSE. I this case, because of the BUS keyword is used i the declaratio of temp, the wirig resolutio fuctio is called with a NULL iput parameter. The defiitio of the wirig fuctio specifies that the iitial value of the accumulate variable (`Z') is retured as the fuctio value if the etire loop statemet i the statemet part of this fuctio is skipped due to a NULL rage. 13

14 9.3.4 Tri-State Buffers 14

15 The block statemet ca be used to defie tri-state logic. To sythesize tri-state devices, Autologic VHDL utilizes the otios of discoect, guarded assigmets, ad resolved bus sigals. Whe the guard expressio of a bus sigal is ot true, the driver is discoected from the target sigal. This meas that other sigals ca drive the target, which requires a resolutio fuctio to resolve the value of the target. The drivig sigal must be of the STD_LOGIC type. The resolved sigal must be of sigal kid bus. The followig illustrates the Autologic VHDL implemetatio of a sigle tri-state buffer: 1 LIBRARY IEEE; 2 USE IEEE.STD_LOGIC_1164.ALL; 3 4 ENTITY triout IS 5 PORT( oe : IN BIT; i : IN STD_LOGIC; 6 o : OUT STD_LOGIC BUS) 7 END triout; 8 9 ARCHITECTURE arch_triout IS 10 tri_out: BLOCK (oe = 1 ) o <= GUARDED i; 13 END BLOCK; 14 END arch_triout; The followig illustrates the CADENCE VHDL implemetatio of a sigle tri-state buffer: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY triout IS PORT( oe : IN bit; i : IN STD_LOGIC; o : OUT STD_LOGIC BUS); END triout; 15

16 ARCHITECTURE arch_triout of triout IS process(oe,i) begi if oe='1' the o<= i ; else o<= 'Z' ; ed if; ed process; END arch_triout; The followig is the Autologic VHDL implemetatio of a bak of four tri-state bufferes: 1 LIBRARY IEEE; 2 USE IEEE.STD_LOGIC_1164.ALL; 3 4 ENTITY tri_buf4 IS 5 PORT (oe : IN STD_LOGIC; 6 i : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 7 o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) BUS); 8 END tri_buf4; 9 10 ARCHITECTURE arch_tri_buf4 OF tri_buf4 IS tri_out: BLOCK (oe = 1 ) 13 o <= GUARDED i; 14 END BLOCK tri_out; END arch_tri_buf4; The followig is the CADENCE VHDL implemetatio of a bak of four tri-state bufferes: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_buf4 IS PORT( oe : IN bit; i : IN STD_LOGIC_VECTOR(3 DOWNTO 0); o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) BUS); END tri_buf4; ARCHITECTURE arch_tri_buf4 of tri_buf4 IS process(oe,i) begi if oe='1' the o<= i ; else o<= "ZZZZ" ; ed if; ed process; END arch_tri_buf4; 16

17 If the target sigal o was ot defied as of kid BUS, a bak of four trasparet latches is implemeted rather tha a bak of four tri-state buffers. 17

18 8.3.5 BUS AND REGISTER SIGNALS The methods for guardig sigals is to specify REGISTER or BUS as the sigal kid i a sigal declaratio. Registers ad buses are automatically guarded sigals. Sigals of the kid register, retai the last output value whe all drivers are discoected. Sigals of the kid bus, re-evaluate the output value whe all drivers are discoected. Evets ad trasactios o the BUS ad REGISTER kid of sigals are exactly the same as log as at least oe driver is tured o. If a evet turs off the last active driver of a guarded sigal, the resolutio fuctio is called for BUS sigals with a NULL parameter; however, it will ot be called if the kid is REGISTER. After all the drivers are tured off, the latter kid of sigals retai their lasr drive value. Example: ENTITY Buses IS GENERIC(Delay:TIME:=0 s); PORT(ct, wr, rd:in STD_LOGIC; dbus:out STD_LOGIC BUS); END Buses; ARCHITECTURE mult_driv OF Buses IS SIGNAL It_bus: STD_LOGIC BUS; b5: BLOCK(ct='1' ) It_bus <= GUARDED reg AFTER Delay s; END BLOCK; b6: BLOCK(wr='1') It_bus <= GUARDED data AFTER Delay s; END BLOCK; b10: BLOCK(rd='1') It_bus <= GUARDED mem AFTER Delay s; END BLOCK dbus<= It_bus; END mult_driv; 18

19 ct reg data wr it_bus mem rd DISCONNECTION SPECIFICATION (NOT supported by Autologic) I the guarded sigal assigmet s<=guarded data AFTER 5 s; If data chages value while the guard expressio is TRUE, the ew value of data will be assiged to s after 5 s. That is, the 5 s delay applies oly whe a driver is coected, or beig coected, ad does ot apply whe a driver is discoected from a guarded sigal. A discoectio specificatio statemet ca be used to specify the discoectio delay for a guarded sigal withi a guarded sigal assigmet. Such a statemet cotais the ame of the sigal, its type, ad a time expressio that specifies the discoectio delay value. To delay the discoectio of the It_bus drivers, the followig statemet should be added to the declarative part of this architecture: DISCONNECT It_bus: STD_LOGIC AFTER 3 s; With the iclusio of this statemet, if a It_bus driver is tured off because its guard expressio becomes FALSE, the effect of this driver remais o It_bus for 3 s after it has bee tured off. The overall effect of this is that the output chages to `Z' 3 s after the last source has bee tured off. Format: DISCONNECT sigal_ame {,sigal_ame}:sigal_ame_type AFTER time_expressio; DISCONNECT OTHERS : sigal_ame_type AFTER time_expressio; DISCONNECT ALL: sigal_ame_type AFTER time_expressio; 19

20 The ALL keyword used for the sigal list implies that the discoectio specificatio applies to all sigals of the type specified. If OTHERS is used i place of the sigal list, the discoectio specificatio applies to sigals of the specified type for which discoectio has ot bee specified i the statemets above this statemet. Example : SIGNAL t: STD_LOGIC BUS; -- guarded sigal declaratio DISCONNECT t: STD_LOGIC AFTER 10 s; discoectio specificatio There is a discoectio specificatio for every guarded sigal, whether you explicitly defie oe or you elect to use the implicit default. The default specificatio is: DISCONNECT guarded_sig_ame:guarded_sig_type AFTER 0 s; 20