Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:
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1 Design of Datapath Controllers and Sequential Logic Lecturer: Date: ACCESS IC LAB
2 Sequential Circuit Model & Timing Parameters ACCESS IC LAB
3 Combinational Logic Review Combinational logic circuits are memoryless No feedback path Output can have multiple logical transitions before settling to correct value Inputs Outputs pp. 3
4 Model of Sequential Circuits Sequential circuits have memory (i.e. remember the past) The output is depend on inputs depend on current state In synchronous system clock orchestrates the sequence of events Fundamental components Combinational circuits Memory elements Current State clock Inputs Combinational Logic Memory Elements Outputs Next State pp. 4
5 Example pp. 5
6 D-FF vs. D-Latch FF is edge sensitive (can be either positive or negative edge) At trigger edge of clock, input transferred to output Latch is level sensitive (can be either active-high or active-low) When clock is active, input passes to output (transparent) When clock is not active, output stays unchanged in out in D Q clk D Q FF clk Latch E out in clk out in clk out pp. 6
7 Important Timing Parameters (1) There is a timing window around the clocking event during which the input must remain stable and unchanged in order to be recognized by flip/flop or latch. Setup Time (T su ) Minimum time before the clocking event by which the input must be stable Hold Time (T h ) Minimum time after the clocking event during which the input must remain stable Propagation Delay (T cq for edge-triggered flip/flop or T dq for latch) Delay overhead of the memory element pp. 7
8 Important Timing Parameters (2) pp. 8
9 System Timing: Minimum Period T > T cq + T logic + T su2 pp. 9
10 System Timing: Minimum Delay Rising edge 1 FF2 T cq,cd + T logic,cd > T hold Make FF2 satisfy the hold time on rising edge pp. 10
11 At some t From The View of Dataflow These computation are simultaneous: B(t) = f AB ( A(t-1) ) C(t) = f BC ( B(t-1) ) D(t) = f CD ( C(t-1) ) pp. 11
12 Simple Sequential Circuit and Verilog Coding ACCESS IC LAB
13 The Sequential always Block Edge-triggered circuits are described using a sequential always block. pp. 13
14 Sensitivity List The use of posedge and negedge makes an always block sequential (edge-triggered) Unlike combinational always block, the sensitivity list does determine the behavior of synthesis pp. 14
15 Synchronous Reset vs.. Asynchronous Reset Synchronous Reset Asynchronous Reset pp. 15
16 Review of Blocking/Nonblocking Assignments Verilog support 2 types of assignments in always block, with subtle different behaviors: Blocking assignment: evaluation and assignment are immediate Nonblocking assignment: all assignment deferred until all righthand sides have been evaluated (end of the virtual timestamp) pp. 16
17 Assignment Styles for Sequential Logic Will nonblocking and blocking assignments both produce the desired result? pp. 17
18 Use Nonblocking for Sequential Logic Blocking assignment do not reflect the intrinsic behavior of multistage sequential logic Guideline: use nonblocking assignment for sequential always block pp. 18
19 Nonblocking vs. Blocking Assignment Nonblocking Blocking pp. 19
20 Use Blocking for Combinational Logic Nonblocking and blocking will both synthesize correctly. Will both simulate correctly? Nonblocking assignment do not reflect the intrinsic behavior of multi-stage combinational logic Guideline: use blocking assignment for combinational always block pp. 20
21 Finite State Machine (FSM) ACCESS IC LAB
22 Finite State Machine Used control the circuit core Partition FSM and non-fsm part Controller Non-FSM Circuit core FSM pp. 22
23 Finite State Machines Synchronous (i.e. clocked) finite state machines (FSMs) have widespread application in digital systems, e.g. as datapath controllers in computational units and processors. Synchronous FSMs are characterized by a finite number of states and by clock-driven state transitions. Mealy Machine: The next state and the outputs depend on the present state and the inputs. Moore Machine: The next state depends on the present state and the inputs, but the output depends on only the present state. Mealy machine Moore machine Inputs Next State and Output Combinational Logic State Register Outputs Inputs Next State Combinational Logic clock State Register Output Combinational Logic Outputs clock pp. 23
24 What is FSM A model of computation consisting of a set of states, (limited number) a start state, input symbols, a transition function that maps input symbols and current states to a next state. pp. 24
25 Memory Elements (ME) Elements of FSM Memorize Current States (CS) Usually consist of FF or latch N-bit FF have 2 n possible states Next-state Logic (NL) Combinational Logic Produce next state Based on current state (CS) and input (X) Output Logic (OL) Combinational Logic Produce outputs (Z) Based on current state, or Based on current state and input pp. 25
26 Output is function of both Input and current state Mealy Machine pp. 26
27 Output is function of CS only Not function of inputs Moore Machine pp. 27
28 Building Behavioral Models of FSM ACCESS IC LAB
29 Modeling FSM in Verilog Sequential Circuits Memory elements of States (CS) Combinational Circuits Next-state Logic (NL) Output Logic (OL) Three coding styles (1) Separate CS, OL and NL (2) Combines NL+ OL, separate CS (3) Combine CS + NL, separate OL pp. 29
30 CS Graduate Institute of Electronics Engineering, NTU Coding Style 1 Separate CS, NL, OL NL OL pp. 30
31 CS Graduate Institute of Electronics Engineering, NTU Coding Style 2 Combine NL+OL; Separate CS NL+OL pp. 31
32 CS+NL Graduate Institute of Electronics Engineering, NTU Coding Style 3 Combine CS+NL; Separate OL OL pp. 32
33 Behavioral Models of FSM Example1 brake=0 accelerator = 0 brake=0 accelerator=1 brake=0 accelerator=1 low speed medium speed brake=0 accelerator = 0 speed = 1 brake=1 brake=1 brake=1 brake=0 accelerator=1 stopped speed = 0 high speed speed = 3 speed = 7 brake=1 brake=x accelerator = 0 brake=0 brake=0 accelerator=1 = x brake accelerator clock speed Note: 1. brake has higher priority 2. Moore machine pp. 33
34 Verilog Coding 1 (CS, NL, OL) module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [2:0] speed; reg [2:0] speed; reg [1:0] curstate, nxtstate; // state encoding parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; // CS ( posedge clock ) curstate <= nxtstate; // OL, Output Logic ( state ) case( state ) stopped: speed = 3 d0; s_low: speed = 3 d1; s_medium: speed = 3 d3; s_high: speed = 3 d7; endcase // NL, Next-state Logic always@( curstate or accelerator or brake ) if ( brake == 1`b1 ) case ( curstate ) stopped: nxtstate = stopped; s_low: nxtstate = stopped; s_medium:nxtstate = s_low; s_high: nxtstate = s_medium; endcase else if ( accelerator == 1`b1 ) case ( curstate ) stopped: nxtstate = s_low; s_low: nxtstate = s_medium; s_medium:nxtstate = s_high; s_high: nxtstate = s_high; endcase else nexstate = curstate; endmodule pp. 34
35 Verilog Coding 2 (CS, NL+OL) module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [2:0] speed; reg [2:0] speed; reg [1:0] curstate, nxtstate; // state encoding parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; // CS ( posedge clock ) current_state <= next_state; // NL + OL, Next-state Logic + Output Logic always@( curstate or accelerator or brake ) if ( brake == 1`b1 ) case ( curstate ) stopped: {speed,nxtstate} = {3 d0,stopped}; s_low: {speed,nxtstate} = {3 d1,stopped}; s_medium:{speed,nxtstate} = {3 d3,s_low}; s_high: {speed,nxtstate} = {3 d7,s_medium}; endcase else if ( accelerator == 1`b1 ) case ( curstate ) stopped: {speed,nxtstate} = {3 d0,s_low}; s_low: {speed,nxtstate} = {3 d1,s_medium}; s_medium:{speed,nxtstate} = {3 d3,s_high}; s_high: {speed,nxtstate} = {3 d7,s_high}; endcase else case ( curstate ) stopped: {speed,nxtstate} = {3 d0,curstate}; s_low: {speed,nxtstate} = {3 d1,curstate}; s_medium:{speed,nxtstate} = {3 d3,curstate}; s_high: {speed,nxtstate} = {3 d7,curstate}; endcase endmodule pp. 35
36 Verilog Coding 3 (CS+NL, OL) module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [2:0] speed; reg [2:0] speed; reg [1:0] curstate; /* nxtstate is removed */ // state encoding parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; // OL, Output Logic ( state ) case( state ) stopped: speed = 3 d0; s_low: speed = 3 d1; s_medium: speed = 3 d3; s_high: speed = 3 d7; endcase // CS + NL, Current State + Next-state Logic always@( posedge clock ) if ( brake == 1`b1 ) case ( curstate ) stopped: curstate <= stopped; s_low: curstate <= stopped; s_medium:curstate <= s_low; s_high: curstate <= s_medium; endcase else if ( accelerator == 1`b1 ) case ( curstate ) stopped: curstate <= s_low; s_low: curstate <= s_medium; s_medium:curstate <= s_high; s_high: curstate <= s_high; endcase /* else is removed since it s edge-trigger block (FF) */ endmodule pp. 36
37 Bad Coding Style (CS+OL+NL) (!!!) module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [2:0] speed; reg [2:0] speed; reg [1:0] curstate; /* nxtstate is removed */ // state encoding parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; speed become edgetriggered variable: synthesis tool translate it into additional FF! always@( posedge clock ) if ( brake == 1`b1 ) case ( curstate ) stopped: {speed,curstate} <= {3 d0,stopped}; s_low: {speed,curstate} <= {3 d1,stopped}; s_medium:{speed,curstate} <= {3 d3,s_low}; s_high: {speed,curstate} <= {3 d7,s_medium}; endcase else if ( accelerator == 1`b1 ) case ( curstate ) stopped: {speed,curstate <= {3 d0,s_low}; s_low: {speed,curstate <= {3 d1,s_medium}; s_medium:{speed,curstate <= {3 d3,s_high}; s_high: {speed,curstate <= {3 d7,s_high}; endcase /* else is removed since it s edge-trigger block (FF) */ endmodule pp. 37
38 State encoding Different state encoding codes will affect Current state register word length Input format of state transition logic Input format of output logic pp. 38
39 Common State Encoding Styles pp. 39
40 Binary FSM pp. 40
41 Onehot FSM pp. 41
42 Comparison of Binary and Onehot Style Binary-encoded FSM fewer flip-flops for state register = log 2 (state number) Onehot-encoded FSM more flip-flops for state register = state number FPGA vender frequently recommend using onehot encoding style because flip-flops are plentiful in FPGA and the combinational logic cells required to implement is less for onehot style. i.e. Onehot style FSM usually runs faster than binary style FSM on FPGA pp. 42
43 A Simple Design Example: Level-to-Pulse Converter A level-to-pulse converter produce a single-cycle pulse each time its input goes high In other words, it s a synchronous rising edge detector Sample application Button and switches (may need de-bounce processing) Single-cycle enable signal for counters pp. 43
44 State Transition Diagram Block diagram of desired system State transition diagram is a useful FSM representation and design aid pp. 44
45 Logic Derivation for a Moore FSM Combinational logic may be derived through Karnaugh map pp. 45
46 Moore Level-to-Pulse Converter pp. 46
47 Design of Mealy Level-to-Pulse Converter pp. 47
48 Mealy Level-to-Pulse Converter FSM s state simply remember the previous value of L Circuit benefits from Mealy FSM s implicit single-cycle assertion of outputs during state transitions pp. 48
49 Trade-Off: Mealy or Moore? Mealy machine response earlier than Moore machine Compare to Moore FSM, Mealy FSM: Be more difficult to conceptualize and design Have fewer states pp. 49
50 FSM Timing Requirements pp. 50
51 Design spec. Example: Vending Machine All selections are 30 cents This machine makes change (dimes and nickels only) Input: 1 coin per clock Q: quarter (25 cents) D: dime (10 cents) N: nickel (5 cents) Output: 1 can or 1 coin per clock DC: dispense can DD: dispense dime DN: dispense nickel pp. 51
52 State Definition pp. 52
53 A Moore Vender pp. 53
54 State Reduction pp. 54
55 Verilog Coding for Moore Vender State register Sequential always block Next-state combinational logic combinational always block with case Output combinational logic combinational always block with case assignment (simple output) pp. 55
56 pp. 56
57 FSM Output Glitching Problem FSM state bits may not transition at precisely the same time Combinational logic for outputs may contain hazard, i.e. result in glitch pp. 57
58 Registered FSM Outputs are Glitch-Free Move output generation into sequential always block Calculate outputs based on next state May increase FSM critical path pp. 58
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