ENGN3213. Digital Systems & Microprocessors. CLAB 1: ICARUS Verilog and ISE WebPACK

Transcription

1 Department of Engineering Australian National University ENGN3213 Digital Systems & Microprocessors CLAB 1: ICARUS Verilog and ISE WebPACK V3.0 Copyright 2010 G.G. Borg ANU Engineering 1

2 Contents 1 CLAB1: Introduction to ICARUS VERILOG and Xilinx ISE WebPACK Aims WINDOWS and the CYGWIN Command Prompt ICARUS VERILOG and GTKWAVE VERILOG For Synthesis: the Multiplexer A VERILOG Test Bench for the Multiplexer A 1-bit Full Adder ISE WebPACK Schematics in ISE VERILOG in ISE Figures

3 1 CLAB1: Introduction to ICARUS VERILOG and Xilinx ISE WebPACK In this lab we will investigate the design and simulation of a multiplexer (MUX) and an ADDER. The aim of the lab is to introduce some important software tools that you will find indispensable in the course and to take a first look at VERILOG HDL. We will use two approaches. In the first part of the lab we will learn to use ICARUS VERILOG and GTKWAVE under WINDOWS. In the second part we will do the same with Xilinx ISE WebPACK. Although we concentrate on simulation in this lab, ISE WebPACK can be used to perform synthesis in hardware. We touch on synthesis in this lab. The lab is rather complex on a first try and you may not understand everything. It will be a good idea to repeat the material at home. Clabs are not assessable and I will be happy to provide extra tutorials if need be. Also remember that whether you continue to use ICARUS VERILOG and/or GTKWAVE again is largely a matter of taste. Although you must know about ICARUS VERILOG you may choose to do all of your project simulations in ISE WebPACK s simulator. Mastering ISE WebPACK is crucial to make progress in this course. Roughly each couple of weeks I will produce a progressive reading brick that repeats the lecture notes in much more detail. To these bricks will be appended the lab notes. You will then be able to attempt the labs in the full context of the theory. 1.1 Aims Learn to use ICARUS VERILOG to simulate hardware described by VERILOG and GTKWAVE to plot the results. Learn to use Xilinx ISE WebPACK 9.2i to create hardware designs in schematics and VERILOG HDL (Hardware Definition Language). Learn to use VERILOG to create combinational logic circuits. Investigate the synthesis of hardware in ISE WebPACK. 1.2 WINDOWS and the CYGWIN Command Prompt First step is to make a directory where you can work under WINDOWS. Create a folder on the H drive. REMEMBER TO USE YOUR FLASH DRIVE TO SAVE ALL YOUR WORK AFTER THE LAB. 3

4 CYGWIN is a UNIX system running under WINDOWS. It produces a command prompt that is much more powerful than the DOS-style prompt under WINDOWS. At home you can also run ICARUS VERILOG from the WINDOWS command prompt as well. Run CYGWIN and navigate to your chosen folder by using the cd (change directory) command as in the following examples. To go to the top of the directory tree type, cd / To go to the H drive type, cd /cygdrive/h To go to the folder above the present folder type, cd.. To execute a binary file mybin in the current folder do,./mybin ret> Whereas to execute it a binary such as notepad in the system folder (usual place to find them under windows) do, notepad ret> To find out where you are use the pwd (Print Working Directory) command and to take a listing of the contents of the current directory type ls. Here is some background on all this. The reason for the./ is that gtkwave is in the local folder. Under unix and windows CMD a. is the name for the current directory and.. for the directory above and under UNIX only / for the root of all directories (the top directory). Also / is the unix directory separator in a concatenated list of directories such as DIR1/DIR2/DIR1/DIR2. Under windows use \. Thus./gtkwave or.\gtkwave.exe are the ways to run gtkwave in unix respectively windows when gtkwave is in the current folder. The gtkwave command also requires all the DLLs to be in the current folder as well. The alternative for a classical WINDOWS install is to copy the binary and all DLLs into the system folder but for some reason gtkwave does not come with an installer. Under LINUX gtkwave does install and so all this./ stuff is unnecessary. ICARUS VERILOG is installed under WINDOWS and so you only need to type iverilog at the command line. This is because the WINDOWS system folder is in the path for binary command execution. Take a few moments to accustom yourself to the CYGWIN command prompt. 4

5 1.3 ICARUS VERILOG and GTKWAVE ICARUS VERILOG has already been installed on the Information Commons and Ian Ross computers. Type the command iverilog ret> to test it out. The CYGWIN window Fig 1 shows the outputs of all the above commands. Next download GTKWAVE from, The file GTKWAVE.zip contains all the files you need to make signal traces from ICARUS VERILOG. Whenever you use GTKWAVE you need all these files in the local directory with your VERILOG code. A folder with all these files downloaded is shown in Fig 2. In order to compile VERILOG source code files under ICARUS VERILOG the following commands must be executed, iverilog myfile.v TB_myfile.v vvp./a.out Here iverilog converts your VERILOG code into a NETLIST. A NETLIST is a standard notation that provides a description of a circuit. The command vvp runs the simulation and produces the files for GTKWAVE. The file myfile.v is the VERILOG code that describes your hardware. The file TB myfile.v is the test bench. To run gtkwave under CYGWIN (assuming that you have a.vcd file in the current folder produced by iverilog),./gtkwave myfile.vcd You ll find it useful to create a.bat file which contains these commands to save unecessary typing. Assuming that the.bat files is named cmp.bat, then to run it just type the following at the CYGWIN command,./cmp.bat Note that again forward slash used by the UNIX command line compared to the backward slash used by the WINDOWS CMD line. For the following exercise down load CLAB1.zip from the following link and unzip it into your local folder. 5

6 1.3.1 VERILOG For Synthesis: the Multiplexer A multiplexer is an electronic switch that allows you to choose one of several inputs and send it unaltered to an output. The truth table of a simple multiplexer is shown below. The sign means a don t care condition. Note that a multiplexer is a combinational circuit according to the definition provided in lectures. X Y Sel Z Truth tables provide a unique representation of a combinational circuit. As you will see in class the Boolean logic representation of a combinational system can be immediately derived from the truth table. Fact: The design of combinational circuits starts with the truth table. The VERILOG source code can be obtained directly from the truth table or the corresponding Boolean expression. A VERILOG module following the truth table may be written as follows, /////////////////////////////////////////////////////////////////////////// module mux16( Z, Sel, X, Y ); input [15:0] X; input [15:0] Y; input Sel; output [15:0] Z; reg [15:0] Z; or Y or Sel) begin case(sel) 1: Z = X; 0: Z = Y; default: Z = 16 hz; endcase end endmodule /////////////////////////////////////////////////////////////////////////// 6

7 The MUX described here in VERILOG is actually a 16 bit MUX. A 16 bit MUX is similar to a 1-bit MUX except that 16 input lines on each of X and Y are connected through to 16 output lines on Z according the 1-bit select valaue, Sel. It is described by a truth table like the one above except that it has 33 inputs and 16 outputs. Take a few moments to understand the code. It is your first example of VERILOG. In a 16-bit MUX all inputs and outputs (except for Sel) are 16-bit wide buses. That is: X,Y and Z are all 16 bits wide. A bus is simply a collection of parallel wires. Each wire carries independent parallel data. Note the syntax used to do this in VERILOG. A bus is defined by a kind of vector declaration: [15:0]. In VERILOG indices start from 0 as in the C programming language. The DEFAULT case of the CASE statement makes Z a 16-bit open circuit output. An output that can be an open circuit (disconnected) as well as a 0 or 1 level is referred to as a tristate output. The operation of the ALWAY S block is as follows. Inside the ALWAY S block is a bunch of objects that take on updated values (in hardware) whenever any one of the variables in the sensistivity list, (XorY orsel), changes. This is how VERILOG handles events as a function of time for combinational circuits. A similar simple construct applies to sequential circuits. Notice that it is an economical description - the only time anything happens is when a change occurs. All inputs likely to change must appear in the sensitivity list of the ALWAY S block. In simple VERILOG for synthesis all events occur instantaneously and in parallel. This is expected because hardware behaves precisely in this way. Compare this to the sequential operation of programming languages like C, BASIC and JAVA. The output Z is a reg variable type in VERILOG because it is on the left hand side in the ALWAY S block. The datatype reg refers to a variable that can retain its value across time steps. This is just what the ALWAY S block needs in order to effect changes in Z 1. In addition to a reg there is one other datatype in VERILOG known as a wire. A wire is a variable which attaches to a reg or another wire. Like real wires, a wire variable is permanent and does not vary with time. All input and output variables in VERILOG are wires. In the schematic equivalent of a circuit, the VERILOG wires may be viewed as interconnecting metallic wires as shown in lectures. A bus is described in VERILOG by either a reg or a wire vector1. The above code is ready for synthesis. ISE WebPACK can be used to implement it in hardware. 1 Note the implication of a reg being some kind of register. An electronic register however is a term describing a volatile memory based on a multi-bit D-type flip flop. The electronic register is not to be confused with the VERILOG datatype reg. Having said this they do have similarities in that reg too imparts memory to an ALWAY S block. Having said this, the VERILOG datatype reg is a language construct which would be but one variable in a complete VERILOG description of a single electronic register. Make sure you understand the difference. 7

8 This is an example of VERILOG for synthesis A VERILOG Test Bench for the Multiplexer To test the MUX for proper operation we need a test bench. A test bench is a VERILOG program that provides stimuli for the VERILOG module under test. The test bench also produces outputs from the test module that can be viewed and analysed. Test bench VERILOG code is only used for simulation. The following is a test bench for the MUX. /////////////////////////////////////////////////////////////////////////// timescale 1 ns/1 ps module TB_mux16; reg [15:0] X; reg [15:0] Y; reg Sel; wire [15:0] Z; mux16 m16( Z, Sel, X, Y ); initial begin $display("\t\t t \t X \t Y \t Sel \ t Z"); #1X <= 16 h0000; #1Y <= 16 hffff; #1Sel <= 1; #1$display("%d \t %b \t %b \t %b \t %b", $time, X,Y,Sel,Z); #1X <= 16 hffff; #1Y <= 16 h0000; #1Sel <= 1; #1$display("%d \t %b \t %b \t %b \t %b", $time, X,Y,Sel,Z); #1X <= 16 h0000; #1Y <= 16 hffff; #1Sel <= 0; #1$display("%d \t %b \t %b \t %b \t %b", $time, X,Y,Sel,Z); #1X <= 16 hffff; #1Y <= 16 h0000; #1Sel <= 0; 8

9 #1$display("%d \t %b \t %b \t %b \t %b", $time, X,Y,Sel,Z); end initial begin $dumpfile("mux16.vcd"); //GTKWAVE stuff $dumpvars; end initial begin: stopat #50; $finish; end end endmodule ////////////////////////////////////////////////////////////////////////// The test bench provides output in two forms: a screen dump provided by the display directive (note the similarity to the C language printf command) and the dumpvars directive which produces.vcd output for GTKWAVE. Another interesting simulation-only construct in the test bench is the #1. The #n tells the simulation to wait n system times (here 1 ns) before executing the command immediately after. Note that this assumes that ICARUS VERILOG is executing the code in a serial fashion. This is clearly only relevant to simulation. Exercise 1. Using a WINDOWS editor such as WORDPAD or PROGRAM- MER S NOTEPAD, save copies of the mux16.v file and its test bench. Using the above cmp.bat simulate the 16-bit multiplexer. You should get an output like that shown in Figs 4 and A 1-bit Full Adder A full adder is an adder with carry-in and carry-out. The truth table of the 1-bit full adder is as follows. 9

10 X Y Cin Z Cout The truth table of the 1-bit full adder The VERILOG for the 1-bit full adder and its test bench may be written as follows ////////////////////////////////////////////////////////////////////////// timescale 1 ns/1 ps module add1(x, Y, Cin, Z, Cout); input X; input Y; input Cin; output Z; output Cout; reg Z; reg Cout; Y, Cin) begin Z =???; Cout =???; end endmodule ////////////////////////////////////////////////////////////////////////// Exercise 2. Fill in the??? code for Z and Cout in the VERILOG for the ADDER ////////////////////////////////////////////////////////////////////////// timescale 1 ns/1 ps 10

11 module TB_add1; reg X; reg Y; reg Cin; wire Z; wire Cout; add1 a1(x, Y, Cin, Z, Cout); initial begin $display("\t\t t \t X \t Y \t Cin \t Z \t Cout"); #1X <= 0; #1Y <= 0; #1Cin <= 0; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 0; #1Y <= 1; #1Cin <= 0; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 1; #1Y <= 0; #1Cin <= 0; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 1; #1Y <= 1; #1Cin <= 0; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 0; #1Y <= 0; #1Cin <= 1; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 0; #1Y <= 1; #1Cin <= 1; 11

12 #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 1; #1Y <= 0; #1Cin <= 1; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); #1X <= 1; #1Y <= 1; #1Cin <= 1; #1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout); end initial begin: stopat $dumpfile("add1.vcd"); $dumpvars; #120; $finish; end endmodule ////////////////////////////////////////////////////////////////////////// Exercise 3. Compare the ICARUS VERILOG screen dump and the GTK- WAVE signal traces for the 1-bit full adder and try to reconcile them. 1.4 ISE WebPACK In this section we are going to look at several aspects of project development with ISE WebPACK (or ISE for short). Specifically 1. Make a 1-bit MUX for synthesis using schematics 2. Implement the 1-bit MUX using VERILOG HDL in ISE 3. Implement the 1-bit adder using VERILOG HDL in ISE The main exercise however is to become accustomed to using ISE. 12

13 1.4.1 Schematics in ISE There are two ways that one will design hardware in this course and both are acceptable approaches. One uses schematics which are hardware blocks with inputs and outputs. Different blocks are interconnected by buses. The other is VERILOG HDL. In practive you will find that VERILOG is the easier of the two methods to apply. However all VERILOG code that you design should be accompanied by at least a hand written schematic. This is because VERILOG for synthesis is all about building hardware and you must know in advance the hardware that will be built by the ISE synthesiser - i.e. the schematic. In this section we will look at how schematics can be handled in ISE. Fig 6 shows a schematic of the 1-bit MUX that we are going to enter into ISE. Inspect the circuit and make sure you understand how it works. It should already be obvious from the previous truth table. To implement the 1-bit MUX in ISE proceed as follows Open ISE from the start menu. Start with New Project under file and choose Schematic from the list. ISE asks you for the project name and folder. Make sure that it is in a suitable place. See Fig Use the values in Fig 9 for this project. This information specifies the hardware. Note that the Top-Level Level Source Type shows Schematic. If you had chosen a VERILOG project then it would read HDL and you would have to add your source code from a text file rather than use the ISE schematic editor to draw a circuit. Working in VERILOG allows you to work off-line outside of ISE. 3. To make a schematic go to Projects New Source and select schematic. See Fig This will create a schematic pane in which you can draw your circuit diagrams. See Fig Browse the categories in search of LOGIC type devices and add two and2 (two input AND gates) devices, one 2or (two input OR gate) and an inv (inverter) as shown in Fig Next add the wires using the WIRE tool and add IO labels. These will be assigned in the next steps to the package pins on the XC2S50 PQ208 FPGA. Also change the IO labels to the more suitable names: X,Y,Sel and Z. See Fig Once you have changed the labels, go to the process pane and start the design rule processes. In particular click on Check Design Rules to check if the circuit has 2 In this exercise we will do the design for a SPARTAN II XC2S50 FPGA. In the hardware labs however the part used in the SPARTAN 3E starter kit is a XC3S500E FPGA 13

14 been connected correctly. Be patient here as this could be a tricky step if you made a mistake in the wire and IO port label entries 3. See Fig Assign the package pins as shown in Fig Look at the contents of the User Constraints File (UCF) as shown in Fig 16. The User Constraints File (UCF) is a text file that contains hardware related information about your ISE project. The UCF can be included with your source files to specify the pin assignments to the FPGA and other hardware specific information. It allows you to bundle your completed projects for ENGN3213 assignments, product deliveries etc. 10. An interesting resource is the FPGA floor planner shown in Figs. 17 and 24. Observe where the inputs and outputs are indicated in the floorplan. The floorplan shows that a single slice has been used in the design. Make sure that you revisit lectures 3 and 4 and your FPGA datasheet to understand how the FPGA has implemented your circuit. 11. Generate the fuse file. The.BIT file is the file you download to the FPGA. The ISE impact tool allows you to download the BIT or fuse file to the FPGA over either the proprietory USB interface or (as in this course) the JTAG cable via the PC printer port. 12. Finally the most useful piece of documentation is the device utilisation summary in the synthesis report as shown in Fig 18. Fig. 19 shows how the XC2S50 slice actually implents the 1-bit MUX as a LUT (Look Up Table) VERILOG in ISE This is the most important section as it shows you how to use VERILOG to design and manufacture hardware. The last section already covered most of what you need to know. First we will use the following VERILOG file of a 1-bit MUX. module mux1( Z, Sel, X, Y ); input X; input Y; input Sel; output Z; 3 In fact this is the weakness of the ISE schematics editor. Generally it is hard to guarantee regular good connections in the GUI. This is a reason why we will avoid ISE schematics in the rest of the course 14

15 reg Z; or Y or Sel) begin Z =???; end endmodule Exercise 4. Use the schematic of Fig 6 to provide the Boolean expression to replace the??? in the ALWAYS block. 1. First close any old projects in ISE. Start with New Project under file and choose HDL from the list and Verilog. ISE asks you for the project name and folder. Make sure that you save them in a suitable place that you can at least locate on the PC. See Figs 20 and Skip through each of the next dialogues. Note however that you could have added your mux1.v here as your VERILOG code should be ready to go before firing up ISE. 3. Now go to Project Add Source and navigate to where you have put mux1.v above and add it to the project. The project should look as shown in Fig Now click on mux1.v in the sources pane. You should see your VERILOG code appear in the right pane as shown in Fig Now all the steps are as above. Assign the package pins in exactly the same manner with exactly the same names as in Fig Run Synthesize XST etc. until all the steps get a green tick. 7. Finally have a look at the FPGA floorplanner, UCF file and the synthesis report. Note how Fig 24 is identical to 17. In future for more complicated VERILOG designs, always view the floorplanner to get an idea of how you are using the hardware. Do not assume that the ISE XST synthesiser will always produce efficient hardware. Try to understand how your VERILOG code determines the routed hardware Exercise 5. We have now developed a 1-bit MUX in ISE. In order to get some practice using ISE, do the same for the 1-bit adder that we previously simulated in ICARUS VERILOG. 15

16 1.5 Figures Figure 1: Figure 2: 16

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18 Figure 5: X Sel Z Y Figure 6: 18

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