The Manual Processor. Lecture 17. Registers: The Multiplexers: The Arithmetic and Logic Unit. The Shifter (This is just a special multiplexer)

Transcription

1 The Manual Processor Lecture 7 In 7 LK Designing a entral Processor Unit: Part : rchitecture and Instructions LK LK Res LU RES Out LKRES Y-out Y-in LK arry Out omputer Hardware Lecture 7 Slide omputer Hardware Lecture 7 Slide2 Registers: The Multiplexers: O U T P U T S S S D Q D Q D Q lock In- I I a b c d a b c d a b c d MUX On- O O S S onnection Oi=Ii(a) Oi=Ii(b) Oi=Ii(c) Oi=Ii(c) I N P U T S omputer Hardware Lecture 7 Slide3 omputer Hardware Lecture 7 Slide4 The rithmetic and Logic Unit The Shifter (This is just a special multiplexer) n- n- f2 f f LU out O O On- f2 f f Function O = O = minus O = minus O = plus O = eor O = or O = and O = - In- I I in f2 f f out On- O O f2 f f Function Oi = Ii (unchanged) Oi = Ii- (left shift) Oi = Ii+ (right shift) Oi = Ii+ (right shift) unchanged left shift with carry arithmetic right shift right shift with carry in omputer Hardware Lecture 7 Slide5 omputer Hardware Lecture 7 Slide6

2 The Manual Processor Execution ycle Executing Instructions Stream Set the multiplexers so that the correct registers are connected together Instruction Pt Instruction Pt2 Unused Insruction Pt Instruction Pt2 Unused etc c cres c Idle c c c c 2 Set the arithmetic hardware to compute the correct function 3 Provide a clock pulse to the registers that are to change omputer Hardware Lecture 7 Slide7 omputer Hardware Lecture 7 Slide Fetching from Memory Idle So why not put the two together Function Generator Output + Get Set MR s2 f2 f f f5 f4 f3 s4 MR c7 Read/Write ddress In MEMORY P MDR MR Read/Write RM lock TS ddress us us 256 by RM 256 by RM &c c s c Res LU Y-out Y-in c3 + MDR c4 s3 P c5 In Out c f f5 s c c s4 ontroller Go c6 To other registers omputer Hardware Lecture 7 Slide9 omputer Hardware Lecture 7 Slide hanges to the Maunal Processor Simple ontroller The Result register now becomes the MDR ready to send data to memory 2 MR can be loaded direct from memory 3 Memory "data out" separated from "data in", and always enabled 4 bits now used as input to the controller Idle State Function Idle Wait for the start signal 2 Load the instruction, 3 Load to Reg 4 Load to Regs and 5 Load the Instruction 6 Load to Regs and MDR 7 Load Result ddress to MR Store the Result Set ddress to get next byte omputer Hardware Lecture 7 Slide omputer Hardware Lecture 7 Slide2

3 Have we done the job? Unfortunately not:- We will never sell a processor that: ontinually needs to read and write to memory 2 Has a large number of execution cycles per instruction 3 Processes only integers up to Has cumbersome 5 byte instructions We need to find ways of speeding it up How can we speed things up hange all the buses from bits to 32 bit, and thus do four times as much in each cycle 2 Provide local registers which can be programmed to store partial results 3 Reduce the size of the combinatorial logic by putting the LU and shifter in parallel omputer Hardware Lecture 7 Slide3 omputer Hardware Lecture 7 Slide4 How can we speed things up real processor at last 4 Design a controller with as small a number of execution cycles as possible 5 Remove elaborate carry arrangements, by doing our arithmetic on big integers R c R c R2 c2 R3 c3 R4 c4 Internal 32 bit us c7 c 32 f4 f3 f2 f f Res LU s3 + P c MR ddress c MEMORY In Out MDR c3 c4 c c4 f f5 s s6 R5 c5 f5 in MSK ontroller R6 out c6 s4 s5 s6 c2 s s s2 c9 omputer Hardware Lecture 7 Slide5 omputer Hardware Lecture 7 Slide6 Problem reak If we wanted to exchange the contents of register R and Register R, what operations must our processor carry out? few observations Registers,, P, MR, MDR, and belong to the hardware designers R //Load from R Registers R, R, R2, R3, R4, R5 and R6 can be manipulated by the programmers R, R //Load R from and from R //at the same time! R //Load R from omputer Hardware Lecture 7 Slide7 omputer Hardware Lecture 7 Slide

4 The ontroller Specification The controller is going to be a finite state machine looking something like this: The ontroller Specification The fetch cycle will get one 32 bit instruction from the memory E3 F The execute cycles will make the processor carry out that instruction Execute E2 E F3 F2 Fetch So, to formalise our specification we need to define what the instructions will do omputer Hardware Lecture 7 Slide9 omputer Hardware Lecture 7 Slide2 The program instructions ssembler instructions are decided between the software specialists and the hardware designers From the software point of view: Instructions should be few but very powerful From the hardware point of view Instructions should be simple and take only a few clock pulses to execute compromise must be found omputer Hardware Lecture 7 Slide2 Memory Reference Instructions LOD Reg, ddress STORE Reg, ddress JUMP ddress LL Reg, ddress LODINDET Reg, Reg2 STOREINDET Reg, Reg2 JUMPINDET Reg LLINDET Reg, Reg2 omputer Hardware Lecture 7 Slide22 Two Register Instructions MOVE Rscr,Rdest DD Rscr,Rdest SUTRT ND OR XOR OMPRE (Subtract but without storing the result) One Register Instructions LER Rdest INREMENT (IN) DEREMENT (DE) OMPLEMENT (OMP) RITHMETI SHIFT LEFT (SL) RITHMETI SHIFT RIGHT (SR) LOGIL SHIFT RIGHT (LSR) RETURN omputer Hardware Lecture 7 Slide23 omputer Hardware Lecture 7 Slide24

5 No Register Instructions SKIP Following an arithmetic or compare operation SKIPPOSITIVE SKIPNEGTIVE NOP Instruction Formats Opcode Rdest ddress Opcode Rdest Rscr Unused Opcode Rdest Unused Opcode Unused omputer Hardware Lecture 7 Slide25 omputer Hardware Lecture 7 Slide26 The Mask Input and Output The memory reference instructions contain a memory address in the bottom 2 bits The mask converts this unsigned 2 bit number to a 32 bit number by masking the top bits This addressing scheme can only cope with 4Mytes, hence the need for indirect memory reference instructions omputer Hardware Lecture 7 Slide27 I 32 I 2 I 2 I 9 I I Gnd O 32 O 2 O 2 O 9 O O Input and output will be achieved using the LOD and STORE instructions Many peripherals, disks, serial ports, etc can be read or written to as if they were memory They can also be connected directly with the memory so that input and output can be done while the processor is otherwise engaged omputer Hardware Lecture 7 Slide2 Register Transfers Memory Reference Instructions We check our design, by determining the register transfers that will be needed to carry out each instruction These register transfers will become the formal specification of the processor controller LOD Rdest, ddress E MR MDR Use the mask E2 MDR Memory E3 Rdest MDR No Mask STORE Rdest, ddress E MR MDR, Rdest Use the mask E2 Memory via the Shifter (no change) JUMP ddress E P MDR Use the mask LL Rdest, ddress E P P+ E2 Rdest P E3 P MDR Use the mask omputer Hardware Lecture 7 Slide29 omputer Hardware Lecture 7 Slide3

6 Indirect Memory Reference Instructions To be continued LODINDET Rscr,Rdest E Rsrc E2 MR E3 MDR Memory E4 Rdest MDR No Mask STOREINDET Rscr,Rdest E Rscr E2 MR ; Rdest via the shifter (no change) E3 Memory via the shifter (no change) JUMPINDET Rscr E Rscr E2 P via the shifter (no change) LLINDET Rscr, Rdest E P P+; Rscr E2 Rdest P; E3 P via the shifter (no change) Don t miss the next thrilling episode omputer Hardware Lecture 7 Slide3 omputer Hardware Lecture 7 Slide32