Lecture Topics ECE 341. Lecture # 10. Register File. Hardware Components of a Processor

Transcription

1 EE 1 Lecture # 10 Instructor: Zeshan hishti zeshan@ece.pdx.edu October 29, 201 Portland State University Lecture Topics asic Processing Unit Hardware omponents path Fetch Section Fetch and Execution Steps Encoding Examples Reference: hapter 5: Sections 5. and 5. (Pages of textbook) Hardware omponents of a Processor ontrol ircuitry Processor Interface P General purpose registers are usually implemented as a register file file contains rray of storage elements to hold register contents ccess circuitry to read/write data from/into any register To support two source operands per instruction ccess circuitry able to read 2 registers at same time inputs & select the registers to be read inputs connected to s source register fields contents available at separate outputs To support a destination operand input selects the register to be written isconnected to s destination register field input used to specify the data to be written For example, for instruction add R, R, R5 =, = 5 and = Reg. s contents Input R0 R1 R2... Rn put Reg. s contents

2 (cont.) memory unit with two output ports is said to be dual ported Two ways to implement a dual-ported register file True ports:single set of registers with duplicate data paths and access circuitry that enables two registers to be read at a time Two copies: Use 2 memory blocks each containing one copy of the register file To read two registers, one register can be accessed from each file To write a register, data needs to be written to both the copies of that register Input rithmetic and Logic Unit () performs: rithmetic operations (adition, subtraction, multiplication etc.) Logic operations (bitwise ND, OR, XOR etc.) file and are connected with each other so that Source operands of an instruction, after being read from the register file are directly fed into the Result computed by the can be loaded into the destination register specified by the instruction put + onnection Hardware omponents of a Processor Source register connected to In input of Multiplexer connected to In input of and the immediate value field in sselect input depends on the instruction being executed selects In, for operations that require only register operands selects immediate valuefor operations that require an immediate operand In In Immediate Value ontrol ircuitry P Processor Interface

3 path Recall that instruction processing consists of fetch phase & execution phase Processor hardware divided into two corresponding sections: Front end (fetch section): Includes the fetch and decode stages ack end (execute section): Includes the, ccess and Writeback stages pathis a combination of register read, back-end stages and inter-stage registers Inter-stage s 1 2 Fetch Decode Execute ccess Writeback R, R,, and are inter-stage registers file is in both stage 2 and stage 5, because stage 2 (Decode) reads source registers and stage 5 (Writeback) writes into destination registers 2 In R R In 2 Front End ack End rithmetic/logic s: 1 source register, 1 immediate operand 2 source registers : carries out the desired arithmetic/logic operation on the source operands, result is loaded into :Result computed in stage- moves from to : transferred from into destination 2 In R R In 2 Load s: Load 1 1 :Effective address computed and loaded into : sent from to memory, data returned by memory loaded into : transferred from into destination 2 In R R In 2

4 Store : Store 1 x :Effective address computed and loaded into, data to be stored is moved from R to : sent from to memory, data sent from to memory, write signal asserted :No action 2 In R R In 2 Subroutine all : saves the subroutine return address (current contents of P) in a destination register Subroutine all x 2 :No action : address sent from P to :ontents of sent to the destination register 2 In R R In 2 Hardware omponents of a Processor Fetch Step ontrol ircuitry P ontrol circuitry examines the contents of and generates the signals needed to control all the processor s hardware ontrol ircuitry (via R) (via ) P Processor Interface Immediate Immediate value (extended to 2 bits) MuxM MuxMselects input 1 during instruction fetch

5 Immediate Field Extension Holds P contents for saving return address during subroutine calls For subroutine call/return, MuxPselects input 0, otherwise it selects input 1 P-Temp R MuxP P dder Immediate Value (ranch Offset) MuxIN For branches, MuxINselects input 1, otherwise it selects input 0 Immediate operand needs to be represented as a 2-bit number before being used as s input Immediate block extends the immediatefield in and sends the extended value to For logical instructions (ND, OR etc.) Immediate value is padded with zeroes to extend from 16 to 2 bits For arithmetic instructions (add, mult etc.) and branches Immediate value is sign-extended from 16 to 2 bits ( ) Encoding Encoding (cont.) 1 Rsrc1 Rsrc2 Rdst Rsrc Rdst (a) -operand format Immediate value Immediate operand (b) Immediate-operand format (c) all format OP code OP code OP code Using a few standard instruction formats simplifies the instruction decoding process The OP code field specifies the type of instruction ontrol circuitry examines the op code to decide which control signals to assert in subsequent stages an the reading of source registers proceed, while the control circuitry is yet to decode the instruction op code? YES, because source register addressesare specified using the same bit positions in all instructions (bits 1-27 and bits 26-22) These two fields in ([1-27] and [26-22]) are connected to address inputs and of register file ontents of these two registers are loaded into R and R at the end of stage 2, irrespective of the type of instruction If these contents are not needed, subsequent stages can ignore them If needed, these contents will be available as operands in stage

6 Example 1:dd R, R, R5 1: address [P], Read memory, data, P [P] + 2: Decode instruction, R [R], R [R5] : [R] + [R] : [] : R [] 2 In R R In 2 Example 2: Load R5, X(R7) 1: address [P], Read memory, data, P [P] + 2: Decode instruction, R [R7] : [R] + Immediate value X : address [], Read memory data : R5 [] 2 In R R In 2 Example : Store R6,X(R8) 1: address [P], Read memory, data, P [P] + 2: Decode instruction, R [R8], R [R6] : [R] + Immediate value X [R] : address, data [], Write memory : No action 2 In R R In 2