Processor Implementation in VHDL. University of Ulster at Jordanstown University of Applied Sciences, Augsburg

Transcription

1 University of Ulster at Jordanstown University of Applied Sciences, Augsburg Master of Engineering VLSI Design Project Report Processor Implementation in VHDL According to Computer Organisation & Design by David A. Patterson and John L. Hennessy Author(s) M. Linder M. Schmid Supervisor(s) J. Färber A. Eder Submitted 6/7/7

2 Document Revision History, Designers Document Revision History Rev. Date Author Description.1 15/5/27 M. Schmid First draft release.2 15/5/27 M. Linder Features of the project.3 29/5/27 M. Linder Target Spec. (2.1, 2.2).4 1/6/27 M. Linder Target Spec. (2.3).5 3/6/27 M. Linder - include jump instruction to Target Spec..6 2/7/27 M. Linder Module Spec. of Data.6.1 2/7/27 M. Schmid Module Spec. of ALU and Memory.6.2 3/7/27 M. Schmid Design Tasks.7 4/7/27 M. Linder - Module Spec. of Datapath - Module Spec. of Control - Synthesis Results - References.8 5/7/27 M. Linder, M. Schmid - Synthesis Results - Source Code - Conclusion 1. 5/7/27 M. Linder, M. Schmid Final release Designer(s) M. Linder michael-linder@web.de M. Schmid martin-werner.schmid@gmx.de Contact Michael Linder Angerstraße 8a Neusäß, Germany Phone +49 () Mail michael-linder@web.de Martin Schmid Fichtenstraße Kutzenhausen, Germany Phone +49 () Mail martin-werner.schmid@gmx.de M. Linder, M. Schmid II

3 Contents Contents 1 2 Introduction Starting from a Simple Implementation Scheme Using Multicycle Implementations Enhancing Performance with Pipelining...2 Target Specification Building a Datapath Major Components Components for Arithmetic and Logic Functions Load word (lw) and store word (sw) instructions Branch on equal instruction Jump Instruction Simple Implementation Scheme Creating a Single Datapath ALU Control Main Control Disadvantages of a Single-Cycle Implementation Multicycle Implementation Additions and Changes in the Scheme Execution of Instructions in Clock Cycles Defining the Control by a Finite State Machine Design Tasks Module Specification ALU Functional Description Block Diagram Simulation Results Design Files Memory Functional Description Block Diagram Simulation Results Design Files M. Linder, M. Schmid III

4 Contents 4.3 Control Functional Description State Diagram Block Diagram Simulation Results Design Files Data Path Instruction Fetch Functional Description Block Diagram Design Files Instruction Decode Functional Description Block Diagram Design Files Execution Functional Description Block Diagram Design Files Memory Writeback Functional Description Block Diagram Design Files Data Path Block Diagram Design Files Processor and Memroy Functional Description Block Diagram Design Files Synthesis Results Results of Prototype Testing Description Simulation Result...49 Conclusion Our own experiences...5 M. Linder, M. Schmid IV

5 Contents Annotations to Computer Organization & Design [PaHe98] Further work on the project...51 Appendix Design files Project Entities Project Architectures Package Testbenches References...91 M. Linder, M. Schmid V

6 Contents List of Figures Figure 1.1 Simple block diagram with datapaths [PaHe98] p Figure 1.2 Multicycle Datapath [PaHe98] p Figure 1.3 Pipelined Version of the Datapath [PaHe98], p Figure 2.1 Instruction Memory, Program Counter and Adder [PaHe98], p Figure 2.2 Datapath for fetching instructions and incrementing the PC [PaHe98] p Figure 2.3 Register and ALU [PaHe98] p Figure 2.4 Datapath for R-type Instructions [PaHe98] p Figure 2.5 Data Memory and Sign extension unit [PaHe98] p Figure 2.6 Load or Store Word instruction field...5 Figure 2.7 Datapath for Load Word and Store Word [PaHe98] p Figure 2.8 Datapath for a branch instruction [PaHe98] p Figure 2.9 Completed Simple Datapath [PaHe98] p Figure 2.1 MIPS field...8 Figure 2.11 Table for ALU Control...8 Figure 2.12 Datapath with ALU Control Unit [PaHe98] p Figure 2.13 Meaning of the main control signals [PaHe98] p Figure 2.14 The simple datapath with the control unit [PaHe98] p Figure 2.15 Truth table of the main control unit [PaHe98] p Figure 2.16 Abstract view of a multicycle desing [PaHe98] p Figure 2.17 Complete Datapath for multicycle design [PaHe98] p Figure 2.18 Actions of 1-bit control signals [PaHe98] p Figure 2.19 Actions of 2-bit control signals [PaHe98] p Figure 2.2 Summary of the multicycle steps [PaHe98] p Figure 2.21 Complete finite state machine control [PaHe98] p Figure 2.22 Setting of Control Signals...2 Figure 4.1 ALU 1/ Figure 4.2 ALU 2/ Figure 4.3 ALU 3/ Figure 4.4 Simulation Results of ALU...26 Figure 4.5 Memory...28 M. Linder, M. Schmid VI

7 Contents Figure 4.6 Simulation Results of Memory (registered outputs)...28 Figure 4.7 Simulation Results of Memory (unregistered outputs)...29 Figure 4.8 Control Finite State Machine...31 Figure 4.9 Control FSM...32 Figure 4.1 ALU Control...32 Figure 4.11 Control...33 Figure 4.12 Simulation Results of the Control FSM...33 Figure 4.13 Instruction Fetch...34 Figure 4.14 Instruction Decode...35 Figure 4.15 Execution...37 Figure 4.16 Memory Writeback... 4 Figure 4.17 Processing Unit (Datapath & Controlpath)...43 Figure 4.18 Processing Unit & Memory...43 Figure 5.1 Analysis & Synthesis Summary...45 Figure 5.2 Analysis & Synthesis Settings...46 Figure 5.3 Compilation History Figure 6.1 Simulation Results of MIPS and Memory M. Linder, M. Schmid VII

8 Contents List of VHDL-Source VHDLSource 8.1 e_control_controlfsm.vhd...52 VHDLSource 8.2 e_control_alucontrol.vhd VHDLSource 8.3 e_control.vhd...52 VHDLSource 8.4 e_tempreg.vhd...53 VHDLSource 8.5 e_pc.vhd...53 VHDLSource 8.6 e_instreg.vhd...53 VHDLSource 8.7 e_regfile.vhd...54 VHDLSource 8.8 e_alu_vhd...54 VHDLSource 8.9 e_data_fetch.vhd...54 VHDLSource 8.1 e_data_decode.vhd...55 VHDLSource 8.11 e_data_execution.vhd...55 VHDLSource 8.12 e_data_memwriteback.vhd VHDLSource 8.13 e_data.vhd...56 VHDLSource 8.14 e_ram.vhd...56 VHDLSource 8.15 e_memory.vhd...57 VHDLSource 8.16 e_mips.vhd...57 VHDLSource 8.17 e_procmem.vhd...57 VHDLSource 8.18 a_control_controlfsm.vhd...6 VHDLSource 8.19 a_control_alucontrol.vhd VHDLSource 8.2 a_control.vhd...62 VHDLSource 8.21 a_tempreg_behave.vhd...63 VHDLSource 8.22 a_pc_behave.vhd...63 VHDLSource 8.23 a_instreg_behave.vhd...64 VHDLSource 8.24 a_regfile_behave.vhd...64 VHDLSource 8.25 a_alu_behave.vhd...65 VHDLSource 8.26 a_data_fetch.vhd...67 VHDLSource 8.27 a_data_decode.vhd...69 VHDLSource 8.28 a_data_execution.vhd...69 VHDLSource 8.29 a_data_memwriteback.vhd... 7 VHDLSource 8.3 a_data.vhd...73 VHDLSource 8.31 a_ram_rtl.vhd...73 M. Linder, M. Schmid VIII

9 Contents VHDLSource 8.32 a_memory_behave.vhd...75 VHDLSource 8.33 a_mips.vhd...77 VHDLSource 8.34 a_procmem.vhd...78 VHDLSource 8.35 p_procmem_definitions.vhd VHDLSource 8.36 t_alu_fileio.vhd...83 VHDLSource 8.37 t_memory.vhd...86 VHDLSource 8.38 t_procmem.vhd...87 M. Linder, M. Schmid IX

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11 1 Introduction 1 Introduction The performance of software systems is dramatically affected by how well software designers understand the basic hardware technologies at work in a system. According to the book Computer Organization & Design written by David A. Patterson and John L. Hennessy the hardware and behaviour of a microprocessor is implemented in VHDL. 1.1 Starting from a Simple Implementation Scheme In the first section starting from a simple implementation scheme of a MIPS subset the basic hardware of the microcontroller s datapath and its control is developed step by step and implemented in VHDL. Testbenches will verify the correct implementation of the arithmetic-logical instructions (add, sub, and, or and slt), the memory-reference instructions (load word and store word) and the branch instructions (beq and jump). Figure 1.1 Simple block diagram with datapaths [PaHe98] p. 352 M. Linder, M. Schmid, 7/7 1

12 1.2 Using Multicycle Implementations 1.2 Using Multicycle Implementations Figure 1.2 Multicycle Datapath [PaHe98] p. 414 Establishing that the efficiency of a long single-cycle implementation is not likely to be very good the processor s speed is improved by using multicycle implementations. Then, instructions are allowed to take different numbers of clock cycles and functional units can be shared within the execution of single instructions. 1.3 Enhancing Performance with Pipelining In order to enhance the performance and to get very fast processors another implementation technique called pipelining is introduced. Multiple instructions are overlapped in execution so that some stages are working in parallel. Figure 1.3 Pipelined Version of the Datapath [PaHe98], p M. Linder, M. Schmid, 7/7

13 2 Target Specification 2 Target Specification 2.1 Building a Datapath Major Components At first we look at the elements required to execute the MIPS instructions and their connection. The first element needed is a place to store the program instructions. This Instruction Memory is used to hold and supply instructions given an address. The address must be kept in the Program Counter (PC), and in order to increment the PC to the address of the next instruction, we also need an Adder. All these elements are shown in figure 2.1. Figure 2.1 Instruction Memory, Program Counter and Adder [PaHe98], p 344 After fetching one instruction from the instruction memory, the program counter has to be incremented so that it points to the address of the next instruction 4 bytes later. This is realised by the datapath shown in figure 2.2. Figure 2.2 Datapath for fetching instructions and incrementing the PC [PaHe98] p. 345 M. Linder, M. Schmid, 7/7 3

14 2.1 Components for Arithmetic and Logic Functions Components for Arithmetic and Logic Functions The instructions we use all read two registers, perform an ALU operation and write back the result. These arithmetic-logical instructions are also called R-type instructions ([PaHe98] p. 154). This instruction class considers add, sub, slt, and and or. The 32 registers of the processor are stored in a Register File. To read a dataword two inputs and two outputs are needed. The inputs are 5 bits wide and specify the register number to be read, the outputs are 32 bits wide and carry the value of the register. To write the result back two inputs are needed one to specify the register number and one to supply the data to be written. The Register is shown in Figure 2.3. Figure 2.3 Register and ALU [PaHe98] p. 346 To process the data from the Register, an ALU with two data inputs is used. Figure 2.4 shows the combination of Register and ALU to operate on R-type instructions. Figure 2.4 Datapath for R-type Instructions [PaHe98] p M. Linder, M. Schmid, 7/7

15 2.1 Load word (lw) and store word (sw) instructions Load word (lw) and store word (sw) instructions Two more elements are needed to implement the sw- and lw-instructions the Data Memory and the Sign Extension Unit. Figure 2.5 Data Memory and Sign extension unit [PaHe98] p. 348 The sw- and lw-instructions compute a memory address by adding a register value to the 16-bit signed offset field contained in the instruction. Because the ALU has 32-bit values, the instruction offset field must be sign extended from 16 to 32 bits simply by concatenating the sign-bit 16 times to the original value. The instruction field for a lw- or sw-instruction is shown in figure 2.6 op 6 bits rs 5 bits rt 5 bits address 16 bits Figure 2.6 Load or Store Word instruction field Figure 2.7 Datapath for Load Word and Store Word [PaHe98] p. 348 M. Linder, M. Schmid, 7/7 5

16 2.1 Branch on equal instruction Branch on equal instruction The beq instruction has three operands, two registers that are compared for equality, and a 16-bit offset used to compute the branch target address relative to the branch instruction address. Figure 2.8 Datapath for a branch instruction [PaHe98] p. 35 Figure 2.8 shows the datapath for a branch on equal instruction. This datapath must do two operations compare the register contents and compute the branch target. Therefore two things must be done The address field of the branch instruction must be sign extended from 16 bits to 32 bits and must be shifted left 2 bits so that it is a word offset. The branch target address is computed by adding the address of the next instruction (PC + 4) to the before computed offset Jump Instruction The jump instruction is similar to the branch instruction, but computes the target PC differently and not conditional. The destination address for a jump is formed by concatenating the upper 4 bits of the current PC + 4 to the 26-bit address field in the jump instruction (see figure 2.1 on page 8) and adding as the last two bits. 6 M. Linder, M. Schmid, 7/7

17 2.2 Simple Implementation Scheme 2.2 Simple Implementation Scheme The simplest possible implementation of the MISP Processor contains the datapath segments explained above added by the required control lines Creating a Single Datapath The simplest datapath might attempt to execute all instructions in one clock cycle. This means that any element can be used only once per instruction. So these elements have to be duplicated. If possible datapath elements can be shared by different instruction flows. Therefore multiple connections to the input must be realised. This is commonly done by a multiplexer. Figure 2.9 shows the combined datapath including a memory of instructions and one for data, the ALU, the PC-unit and the mentioned multiplexers. Figure 2.9 Completed Simple Datapath [PaHe98] p. 353 M. Linder, M. Schmid, 7/7 7

18 2.2 ALU Control ALU Control The MIPS field that contains the information about the instruction has the following structure op 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits Desired ALU action ALU control input Figure 2.1 MIPS field The meaning of the fields are op basic operation rs first register source rt second register source rd register destination shamt shift amount funct function Instruction opcode ALUOp Instruction operation Funct field LW load word XXXXXX add 1 SW store word XXXXXX add 1 Branch equal 1 branch equal XXXXXX subtract 11 R-type 1 add 1 add 1 R-type 1 subtract 11 subtract 11 R-type 1 AND 11 and R-type 1 OR 111 or 1 R-type 1 set on less than 111 set on less than 111 Figure 2.11 Table for ALU Control Figure 2.11 shows in the last column the 3-bit ALU control input. It depends on the 6-bit funct field of the MIPS instruction and the 2-bit ALUOp signal generated form the Main Control Unit (see Chapter 2.2.3). Figure 2.12 shows the datapath including the ALU Control Unit. 8 M. Linder, M. Schmid, 7/7

19 2.2 ALU Control Figure 2.12 Datapath with ALU Control Unit [PaHe98] p Main Control The main control unit generates the control bits for the multiplexers, the data memory and the ALU control unit. The input of the main control unit is the 6-bit op-field of the MIPS instruction field (see figure 2.9 on page 7). Figure 2.13 shows the meaning of the several control signals. Signal name Effect when deasserted Effect when asserted RegDst The register destination number for the Write register comes from the rt field (bits 2-16). The register destination number for the Write register comes from the rd field (bits 15-11). RegWrite None The register on the Write register input is written with the value on the Write data input. ALUSrc The second ALU operand comes from the second register file output (Read data 2). The second ALU operand is the sign-extended, lower 16 bits of the instruction. PCSrc The PC is replaced by the output of the adder that computes the value of PC + 4. The PC is replaced by the output of the adder that computes the branch target. MemRead None Data memory contents designated by the address input are put on the Read data output. MemWrite None Data memory contents designated by the address input are replaced by the value on the Write data input. MemtoReg The value fed to the register Write data input comes from the ALU. The value fed to the register Write data input comes from the data memory. Figure 2.13 Meaning of the main control signals [PaHe98] p. 359 M. Linder, M. Schmid, 7/7 9

20 2.2 Main Control The connection of the main control unit is shown in figure This and the meaning of the signals described in figure 2.13 leads directly to the truth table for the main control unit shown in figure Figure 2.14 The simple datapath with the control unit [PaHe98] p. 36 RegDst ALUSrc MemtoReg Reg Write Mem Read Mem Write Branch ALUOp1 ALUOp lw sw X 1 X 1 beq X X 1 1 Instruction R-format Figure 2.15 Truth table of the main control unit [PaHe98] p Disadvantages of a Single-Cycle Implementation In modern designs a single cycle implementation of a processor is not used, because it is inefficient. A clock cycle must have the same length for every instruction and therefore it is determined by the longest possible path. Almost this is the path of the load word instruction which uses five functional units in series the instruction memory, the register file, the ALU, the data memory and the register file again. However a single cycle implementation can be used for a small instruction set. But if the machine gets more powerful there can be used thousands of functional units and then the longest path causes the cycle time. 1 M. Linder, M. Schmid, 7/7

21 2.3 Multicycle Implementation 2.3 Multicycle Implementation To avoid the disadvantages of the single cycle implementation described in the section before, a multicycle implementation is used. This technique divides each instruction into steps and each step is executed in one clock cycle. The multicycle implementation allows a functional unit to be used more than once in a instruction, so that the number of functional units can be reduced. The major advantage of a multicycle design is the ability to share functional units within an execution Additions and Changes in the Scheme Figure 2.16 shows a abstract design of a multicycle datapath. Figure 2.16 Abstract view of a multicycle desing [PaHe98] p. 378 Comparing to the single-cycle datapath the differences are that only one memory unit is used for instructions and data, there is only one ALU instead of an ALU and two adders and several output registers are added to hold the output value of a unit until it is used in a later clock cycle. The instruction register (IR) and the memory data register (MDR) are added to save the output of the memory. The registers A and B hold the register operands read form the register file and the ALUOut holds the output of the ALU. With exception of the IR all these registers hold data only between a pair of adjacent clock cycles. M. Linder, M. Schmid, 7/7 11

22 2.3 Additions and Changes in the Scheme Because the IR holds the value during the whole time of the execution of a instruction, it requires a write control signal. The reduction from former three ALUs to one causes also the following changes in the datapath An additional multiplexer is added for the first ALU input to choose between the A register and the PC. The multiplexer at the second ALU input is changed from a two-way to a fourway multiplexer. The two new inputs are a constant 4 to increment the PC and the sign-extended and shifted offset field for the branch instruction. In order to handle branches and jumps more additions in the datapath are required. The three cases of R-type instructions, branch instruction and jump instruction cause three different values to be written into the PC The output of the ALU which is PC + 4 should be stored directly to the PC. The register ALUOut after computing the branch target address. The lower 26 bits of the IR shifted left by two and concatenated with the upper 4 bits of the incremented PC, when the instruction is jump. If the instruction is branch, the write signal for the PC is conditional. Only if the the two compared registers are equal, the computed branch address has to be written to the PC. Therefore the PC needs two write signals, which are PCWrite if the write is unconditional (value is PC + 4 or jump instruction) and PCWriteCond if the write is conditional. 12 M. Linder, M. Schmid, 7/7

23 2.3 Additions and Changes in the Scheme Figure 2.17 shows the completed datapath for a multicycle implementation including the whole control. It also shows that the write signal for the PC is combined form the ALU zero bit and the two write signals PCWrite and PCWriteCond by an AND gate and OR gate. Figure 2.17 Complete Datapath for multicycle design [PaHe98] p. 383 M. Linder, M. Schmid, 7/7 13

24 2.3 Execution of Instructions in Clock Cycles Execution of Instructions in Clock Cycles The execution of an instruction is broken into clock cycles, that means that each instruction is divided into a series of steps. Therefore the setting of the control signals are shown in figures 2.18 and Signal name Effect when deasserted Effect when asserted RegDst The register file destination number for the Write register comes from the rt field The register file destination for the Write register comes from the rd field RegWrite None The general-purpose register selected by the Write register number is written with the value of the Write data input. ALUSrcA The first ALU operand is the PC The first ALU operand comes from the A register MemRead None Content of memory at the location specified by the Address input is put on Memory data output. MemWrite None Memory contents at the location specified by the Address input is replaced by value on Write data input. MemtoReg The value fed to the register file Write data input comes from ALUOut. The value fed to the register file Write data input comes from the MDR. IorD The PC is used to supply the address to the memory unit. ALUOut is used to supply the address to the memory unit. IRWrite None The output of the memory is written into the IR. PCWrite None The PC is written the source is controlled by PCSource. PCWriteCond None The PC is written if the Zero output from the ALU is also active. Figure 2.18 Actions of 1-bit control signals [PaHe98] p. 384 Signal name ALUOp ALUSrcB PCSource Value Effect The ALU performs an add operation. 1 The ALU performs an subtract operation. 1 The function field of the instruction determines the ALU operation. The second input to the ALU comes from the B register. 1 The second input to the ALU is the constant 4. 1 The second input to the ALU is the sign-extended, lower 16 bits of the IR. 11 The second input to the ALU is the sign-extended, lower 16 bits of the IR shifted left 2 bits. Output of the ALU (PC + 4) is sent to the PC for writing. 1 The contents of ALUOut (the branch target address) are sent to the PC for writing. 1 The jump target address (IR[25-] shifted left 2 bits and concatenated with PC +4[31-28]) is sent to the PC for writing. Figure 2.19 Actions of 2-bit control signals [PaHe98] p M. Linder, M. Schmid, 7/7

25 2.3 Execution of Instructions in Clock Cycles The execution of an instruction is divided into maximal five steps. Different elements of the datapath can work in parallel during one clock cycle, whereas others can only be used in series. So there must be sure, that after one step the values computed are stored either in the memory or in one of the registers. The operation steps are 1. Instruction fetch step Fetch the instruction from the memory and computed the address of the sequential instruction IR = Memory[PC] PC = PC + 4 Control signal setting MemRead = 1 IRWrite = 1 IorD = ALUSrcA = 1 ALUSrcB = 1 ALUOp = PCSource = PCWrite = 1 2. Instruction decode and register fetch step It is still unknown what the instruction is, so there can only be performed actions that are applicable for all instructions or are not harmful. The registers indicated by the rs and rd field of the instruction are read and store into the A and B register, and the potential branch target is computed and stored into the ALUOut register. A = Reg[IR[25-21]] B = Reg[IR[2-16]] ALUOut = PC + (sign-extend (IR[15-]) << 2) Control signal setting ALUSrcA = ALUSrcB = 11 ALUOp = M. Linder, M. Schmid, 7/7 15

26 2.3 Execution of Instructions in Clock Cycles 3. Execution, memory address computation or branch completion In this step the instruction is known and the operation depends on what the instruction is. One of these four functions is executed 1. Memory reference ALUOut = A + sign-extend(ir[15-]) Control signal setting ALUSrcA = 1 ALUSrcB = 1 ALUOp = 2. Arithmetic-logical instruction ALUOut = A op B Control signal setting ALUSrcA = 1 ALUSrcB = ALUOp = 1 3. Branch if (A == B) PC = ALUOut Control signal setting ALUSrcA = 1 ALUSrcB = ALUOp = 1 PCWriteCond = 1 PCSource = 1 4. Jump PC = PC[31-28] & (IR[25-] << 2) Control signal setting PCWrite = 1 16 M. Linder, M. Schmid, 7/7

27 2.3 Execution of Instructions in Clock Cycles 4. Memory access or R-type instruction completion step In this step a load or store instruction accesses memory or a arithmeticlogical instruction writes its result. 1. Memory reference MDR = Memory [ALUOut] or Memory [ALUOut] = B Control signal setting MemRead = 1 or MemWrite = 1 IorD = 1 2. Arithmetic-logical instruction Reg[IR[15-11]] = ALUOut Control signal setting RegDst = 1 RegWrite = 1 MemtoReg = 5. Memory read completion step The load instruction is completed by writing back the value from the memory Reg[IR[2-16]] = MDR Control signal setting MemtoReg = 1 RegWrite = 1 RegDst = These five steps are summarised in figure 2.2. M. Linder, M. Schmid, 7/7 17

28 2.3 Execution of Instructions in Clock Cycles Step name Action for R-type instructions Action for memoryreference instructions Instruction fetch Action for branches Action for jumps IR = Memory[PC] PC = PC + 4 Instruction decode register fetch A = Reg[IR[25-21]] B = Reg[IR[2-16]] ALUOut = PC + (sign-extend(ir[15-] << 2) Execution, address computation, branch/jump completion ALUOut = A op B ALUOut = A + sign-extend (IR[15-]) Memory access or Rtype completion Reg[IR[15-11]] = ALUOut Load MDR = Memory[ALUOut] or Store Memory[ALUOut] = B Memory read completion if (A == B) then PC = ALUOut PC = PC[31-28] (IR[25-] << 2) Load Reg[IR[2-16]] = MDR Figure 2.2 Summary of the multicycle steps [PaHe98] p Defining the Control by a Finite State Machine In the single step implementation the control was defined by simple truth tables that set the control signals depending on the instruction. This does not work for a mulitcycle datapath. The control is more complex, because it must specify both the signals to be set in any step and the next step in the sequence. Therefore a finite state machine is used. Figure 2.21 shows the finite state machine for the control of the multicycle datapath implementation. 18 M. Linder, M. Schmid, 7/7

29 2.3 Defining the Control by a Finite State Machine Figure 2.21 Complete finite state machine control [PaHe98] p. 396 The setting of the control signals is also shown in figure All unused signals have to be deasserted or keep their value during the next states until they are set again. All signal settings in all states is shown in figure M. Linder, M. Schmid, 7/7 19

30 2.3 Defining the Control by a Finite State Machine Signal name State RegDst 1 RegWrite 1 1 ALUSrcA MemRead 1 1 MemWrite 1 MemtoReg 1 IorD 1 1 IRWrite 1 PCWrite 1 1 PCWriteCond 1 ALUOp ALUSrcB PCSource 1 1 Figure 2.22 Setting of Control Signals 2 M. Linder, M. Schmid, 7/7

31 3 Design Tasks 3 Design Tasks Block Diagram of first hierarchy levels Register Transfer Level Models implemented in pure VHDL VHDL Testbench of important RTL Models Implementation in Altera Target Technology Prototype Testing Simulation Tool ModelSim Synthesis Tool Altera Quartus Milestone Presentations Design Project Report in OpenOffice Document Format Design Directory Structure is mandatory according to the following table Object Description toplevel Root directory for a VHDL design project toplevel/src directory for VHDL source code toplevel/work directory for VHDL working library, contains compiled object code of ModelSim VHDL compiler toplevel/simulation simulation results toplevel/stimuli stimuli files of extended simulation runs should be stored in this directory toplevel/pnr data produced after a place&route run can be found in this directory toplevel/scripts scriptfiles for automated batch processing of the design steps should be placed here toplevel/log log files of the different design steps toplevel/doc directory for project documentation, data sheets, etc. M. Linder, M. Schmid, 7/7 21

32 4 Module Specification 4 Module Specification 4.1 ALU Functional Description The arithmetic-logic unit (ALU) performs basic arithmetic and logic operations which are controlled by the opcode. The result of the instruction is written to the output. An additional zero-bit signalizes an high output if the result equals zero. At the present time, the basic arithmetic operations add and sub and the logic operations and, or and slt can be applied to inputs. The inputs are 32 bit wide with type unsigned. A detection of overflow or borrow is not supported at the moment. 22 M. Linder, M. Schmid, 7/7

33 4.1 Block Diagram Block Diagram Figure 4.1 ALU 1/3 M. Linder, M. Schmid, 7/7 23

34 4.1 Block Diagram Figure 4.2 ALU 2/3 24 M. Linder, M. Schmid, 7/7

35 4.1 Block Diagram Figure 4.3 ALU 3/3 M. Linder, M. Schmid, 7/7 25

36 4.1 Simulation Results Simulation Results Figure 4.4 Simulation Results of ALU Design Files File Name File Type Description e_alu.vhd a_alu_behave.vhd VHDL Source Files Arithmetic-logic unit t_alu.vhd VHDL Testbench File Testbench for single operations t_alu_fileio.vhd VHDL Testbench File Testbench using file I/O 26 M. Linder, M. Schmid, 7/7

37 4.2 Memory 4.2 Memory Functional Description Data is synchronously written to or read from the memory with a data bus width of 32 bit. The memory consists of four ram blocks with 8 bit data width each. A control signal enables the memory to be written, otherwise data is only read. In order to store data to the memory the data word is subdivided into four bytes which are separately written to the ram blocks. Vice versa, the single bytes are concatenated to get the data word back again. At the moment, it is only possible to read and write data words. An addressing of half-words or single bytes is not allowed. In order to write or read data words, all ram blocks have to be selected. Hence, the lowest two bit are not examined for chip-select logic. Data is addressed by the MIPS-processor with an address width of 32 bit, while the address width of a ram block is 8 bit each. All ram blocks are connected to the same address, namely from mem_address(9 downto 2). Since we do not use the full address width for addressing and chip selects, data words are addressed by multiple addresses. Unfortunately, some problems occurred during simulation of the memory unit. According to the MIPS design shown in literature [PaHe98], there should be implemented a memory unit with an unregistered output. The Altera Quartus MegaWizard Plug-In Manager yielded a ram block with a synchronous output (a_ram_syn.vhd), although the output was defined as unregistered. In order to get an unregistered memory output, another ram block was defined in VHDL code (a_ram_rtl.vhd). There, the output directly yields the data being addressed by the unregistered input address. Unfortunately, the synthesizer does not support memory initialisation files in the RTL-code for setting data to the memory. Hence, it was not possible to implement the memory in real hardware. M. Linder, M. Schmid, 7/7 27

38 4.2 Block Diagram Block Diagram Figure 4.5 Memory Simulation Results Figure 4.6 shows the simulation results with registered data output. Figure 4.6 Simulation Results of Memory (registered outputs) 28 M. Linder, M. Schmid, 7/7

39 4.2 Simulation Results Figure 4.7 shows the simulation results with unregistered output. Note that the simulation contains unknown values, because the memory initialisation files are not supported. Figure 4.7 Simulation Results of Memory (unregistered outputs) Design Files File Name File Type Description e_ram.vhd a_ram_rtl.vhd a_ram_syn.vhd a_ram_lpm.vhd VHDL Source Files Ram block used as component for memory instantiation e_memory.vhd a_memory_behave.vhd VHDL Source Files Instantiation and connection of ram blocks t_memory.vhd VHDL Testbench Files Test memory read. write and address./simulation/ram_256x8.hex./simulation/ram1_256x8.hex./simulation/ram2_256x8.hex./simulation/ram3_256x8.hex Intel Hex Format Files Used for memory initialisation (a_ram_syn.vhd) M. Linder, M. Schmid, 7/7 29

40 4.3 Control 4.3 Control Functional Description The control of the processor is realised by a Finite State Machine described in section The input to the State Machine are the upper 6 bits of the function field containing the instruction. The outputs of the state machine are the control signals of the single functional units of the processor implementation especially the multiplexers of the datapath. The Operation Code of the ALU is stored in a truth table and the corresponding Opcode is produced depending on the ALUOp signal of the state machine and the lower 6 bits of the function field containing the information which of the arithmetic or logic instruction is to use. 3 M. Linder, M. Schmid, 7/7

41 4.3 State Diagram State Diagram ErrorState Figure 4.8 Control Finite State Machine An additional Error State is inserted which is a deadlock. If any unknown instruction occurs the Error State is entered. M. Linder, M. Schmid, 7/7 31

42 4.3 Block Diagram Block Diagram Figure 4.9 Control FSM Figure 4.1 ALU Control 32 M. Linder, M. Schmid, 7/7

43 4.3 Block Diagram Figure 4.11 Control Simulation Results Figure 4.12 Simulation Results of the Control FSM Design Files File Name File Type Description e_control_controlfsm.vhd a_control_controlfsm.vhd VHDL Source Files Finite State Machine for Control e_control_alucontrol.vhd a_control_alucontrol.vhd VHDL Source Files Truth Tabel for ALU Control e_control.vhd a_control.vhd VHDL Source Files Controlpath M. Linder, M. Schmid, 7/7 33

44 4.4 Data Path 4.4 Data Path The datapath is divided into four sections with respect to the pipelining structure of a processor. The four parts are the Instruction Fetch, Instruction Decode, Execution and Memory Writeback. These sections are synthesized of their own and then combined to the Data Block Instruction Fetch Functional Description The Instruction Fetch Block contains the PC the Instruction Register and the Memory Data Register. This part provides the data and instruction form the memory Block Diagram Figure 4.13 Instruction Fetch 34 M. Linder, M. Schmid, 7/7

45 4.4 Instruction Fetch Design Files File Name File Type Description e_pc.vhd a_pc_behave.vhd VHDL Source Files Program Counter e_tempreg.vhd a_tempreg_behave.vhd VHDL Source Files Temporary Memory Data Register e_instreg.vhd a_instreg_behave.vhd VHDL Source Files Instruction Register e_data_fetch.vhd a_data_fetch_behave_vhd VHDL Source Files Instruction Fetch Block Instruction Decode Functional Description The Instruction Decode Block writes the instruction of the Instruction Register to the Register File and computes the second operand for a Branch Instruction or a sw- or lw-instruction Block Diagram Figure 4.14 Instruction Decode M. Linder, M. Schmid, 7/7 35

46 4.4 Instruction Decode Design Files File Name File Type Description e_regfile.vhd a_regfile_behave.vhd VHDL Source Files Register File e_tempreg.vhd a_tempreg_behave.vhd VHDL Source Files Temporary Memory Data Register e_data_decode.vhd a_data_decode_behave.vhd VHDL Source Files Data Decode Block Execution Functional Description The Execution contains the ALU as main element and computes the desired result of the instruction. It also computes the jump target address and provides it for the Memory Writeback Block. The operands loaded to the ALU are chosen by two multiplexers which are sensible to the signals ALUSrcA and ALUSrcB. 36 M. Linder, M. Schmid, 7/7

47 4.4 Execution Block Diagram Figure 4.15 Execution M. Linder, M. Schmid, 7/7 37

48 4.4 Execution Design Files File Name File Type Description e_alu.vhd a_alu_behave.vhd VHDL Source Files ALU e_data_execution.vhd a_data_execution.vhd VHDL Source Files Execution Block 38 M. Linder, M. Schmid, 7/7

49 4.4 Memory Writeback Memory Writeback Functional Description The Memory Writeback Block consists of the ALUOut register and a multiplexer with source signal PCSource. This block leads the result of the computation either back to memory or to the register file. The multiplexer leads back the next PC value depending on the PCSource signal. M. Linder, M. Schmid, 7/7 39

50 4.4 Memory Writeback Block Diagram Figure 4.16 Memory Writeback 4 M. Linder, M. Schmid, 7/7

51 4.4 Memory Writeback Design Files File Name File Type Description e_tempreg.vhd a_tempreg_behave.vhd VHDL Source Files Temporary ALUOut Register e_data_memwriteback.vhd a_data_memwriteback.vhd VHDL Source Files Memory Writeback Block M. Linder, M. Schmid, 7/7 41

52 4.4 Data Path Data Path Block Diagram Design Files File Name File Type Description e_data.vhd a_data_vhd VHDL Source Files Datapath e_data_fetch.vhd a_data_fetch.vhd VHDL Source Files Data Fetch Block e_data_decode.vhd a_data_decode.vhd VHDL Source Files Data Decode Block e_data_execution.vhd a_data_execution.vhd VHDL Source Files Data Execution Block e_data_memwriteback.vhd a_data_memwriteback.vhd VHDL Source Files Memory Writeback Block e_tempreg.vhd a_tempreg_behave.vhd VHDL Source Files Temporary ALUOut Register e_alu.vhd a_alu_behave.vhd VHDL Source Files ALU e_regfile.vhd a_regfile_behave.vhd VHDL Source Files Register File e_pc.vhd a_pc_behave.vhd VHDL Source Files Program Counter e_instreg.vhd a_instreg_behave.vhd VHDL Source Files Instruction Register 42 M. Linder, M. Schmid, 7/7

53 4.5 Processor and Memroy 4.5 Processor and Memroy Functional Description The both parts Datapath and Controlpath are combined to the processing unit. Together with the Memory the whole processor is completed Block Diagram Figure 4.17 Processing Unit (Datapath & Controlpath) Figure 4.18 Processing Unit & Memory M. Linder, M. Schmid, 7/7 43

54 4.5 Design Files Design Files File Name File Type Description e_control_controlfsm.vhd a_control_controlfsm.vhd VHDL Source Files Finite State Machine for Control e_control_alucontrol.vhd a_control_alucontrol.vhd VHDL Source Files Truth Tabel for ALU Control e_control.vhd a_control.vhd VHDL Source Files Controlpath e_data.vhd a_data.vhd VHDL Source Files Datapath e_data_fetch.vhd a_data_fetch.vhd VHDL Source Files Data Fetch Block e_data_decode.vhd a_data_decode.vhd VHDL Source Files Data Decode Block e_data_execution.vhd a_data_execution.vhd VHDL Source Files Data Execution Block e_data_memwriteback.vhd a_data_memwriteback.vhd VHDL Source Files Memory Writeback Block e_tempreg.vhd a_tempreg_behave.vhd VHDL Source Files Temporary ALUOut Register e_alu.vhd a_alu_behave.vhd VHDL Source Files ALU e_regfile.vhd a_regfile_behave.vhd VHDL Source Files Register File e_pc.vhd a_pc_behave.vhd VHDL Source Files Program Counter e_instreg.vhd a_instreg_behave.vhd VHDL Source Files Instruction Register e_ram.vhd a_ram_rtl.vhd a_ram_syn.vhd a_ram_lpm.vhd VHDL Source Files Ram block used as component for memory instantiation t_procmem.vhd t_procmem_init.vhd VHDL Testbench Files Testbench for testing the processor 44 M. Linder, M. Schmid, 7/7

55 5 Synthesis Results 5 Synthesis Results Analysis & Synthesis Summary Analysis & Synthesis Status Successful - Thu Jul Quartus II Version 7. Build 33 2/5/27 SJ Full Version Revision Name procmem Top-level Entity Name procmem Family Cyclone II Total logic elements Total combinational functions Dedicated logic registers Total registers Total pins 2 Total virtual pins Total memory bits Embedded Multiplier 9-bit elements Total PLLs Figure 5.1 Analysis & Synthesis Summary Analysis & Synthesis Settings Option Setting Default Value Device EP2C2F484C7 Top-level entity name procmem procmem Family name Cyclone II Stratix Restructure Multiplexers Auto Auto Create Debugging Nodes for IP Cores Off Off Preserve fewer node names On On Disable OpenCore Plus hardware evaluation Off Off Verilog Version Verilog_21 Verilog_21 VHDL Version VHDL93 VHDL93 State Machine Processing Auto Auto Safe State Machine Off Off Extract Verilog State Machines On On Extract VHDL State Machines On On Ignore Verilog initial constructs Off Off Add Pass-Through Logic to Inferred RAMs On On DSP Block Balancing Auto Auto NOT Gate Push-Back On On Power-Up Don't Care On On Remove Redundant Logic Cells Off Off Remove Duplicate Registers On On Ignore CARRY Buffers Off Off Ignore CASCADE Buffers Off Off Ignore GLOBAL Buffers Off Off Ignore ROW GLOBAL Buffers Off Off Ignore LCELL Buffers Off Off Ignore SOFT Buffers On On Limit AHDL Integers to 32 Bits Off Off Optimization Technique -- Cyclone II Balanced Balanced Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II 7 7 Auto Carry Chains On On Auto Open-Drain Pins On On Perform WYSIWYG Primitive Resynthesis Off Off Perform gate-level register retiming Off Off Allow register retiming to trade off Tsu/Tco with Fmax On On Auto ROM Replacement On On Auto RAM Replacement On On Auto Shift Register Replacement On On Auto Clock Enable Replacement On On Allow Synchronous Control Signals On On Force Use of Synchronous Clear Signals Off Off Auto RAM to Logic Cell Conversion Off Off Auto Resource Sharing Off Off Allow Any RAM Size For Recognition Off Off Allow Any ROM Size For Recognition Off Off Allow Any Shift Register Size For Recognition Off Off Ignore translate_off and synthesis_off directives Off Off Show Parameter Settings Tables in Synthesis Report On On Ignore Maximum Fan-Out Assignments Off Off M. Linder, M. Schmid, 7/7 45

56 5 Synthesis Results Retiming Meta-Stability Register Sequence Length 2 2 PowerPlay Power Optimization Normal compilation Normal compilation HDL message level Level2 Level2 Suppress Register Optimization Related Messages Off Off Number of Removed Registers Reported in Synthesis Report 1 1 Use smart compilation Off Off Figure 5.2 Analysis & Synthesis Settings Compilation Hierarchy procmem mips controlinst_control ALUControlinst_ALUControl ControlFSMinst_ControlFSM datainst_data data_decodeinst_data_decode regfileinst_regfile temprega tempregb data_executioninst_data_execution alualu_inst data_fetchinst_data_fetch instreginstr_reg pcproc_cnt tempregmem_data_reg data_memwritebackinst_data_memwriteback tempregtempreg_inst memory rammem_block altsyncramram_block_rtl_ altsyncram_ia61auto_generated rammem_block1 altsyncramram_block_rtl_1 altsyncram_ia61auto_generated rammem_block2 altsyncramram_block_rtl_2 altsyncram_ia61auto_generated rammem_block3 altsyncramram_block_rtl_3 altsyncram_ia61auto_generated Figure 5.3 Compilation History 46 M. Linder, M. Schmid, 7/7

57 6 Results of Prototype Testing 6 Results of Prototype Testing 6.1 Description For the first test of the completed processor and the memory a simple addition of two numbers was done. Therefore at first the memory has to be loaded with the instructions and data by using *.mif-files to write the information into the memory blocks before starting the simulation. The instructions written into the memory are Memory Instruction Field Address Instruction op rs rt lw $s, 128($zero) lw $s1, 132($zero) add $s2, $s, $s sw $s2, 136($zero) sub $s3, $s1, $s sw $s3, 14($zero) and $s4, $s1, $s sw $s4, 144($zero) or $s5, $s1, $s sw $s5, 148($zero) slt $s6, $s1, $s sw $s6, 152($zero) beq $s, $s4, UNDEFINED UUUUUU UUUUU UUUUU 56 j8 1 rd shamt funct UUUUU UUUUU UUUUUU 1 The data written to the memory are Memory Address Data (dec) Data (bin) M. Linder, M. Schmid, 7/7 47

58 6.1 Description The expected values stored back into the memory are Memory Address Data (dec) Data (bin) The simulation starts at memory address with a load word instruction. The value of memory address 128 is written into register $s. The PC is incremented and the next instruction of memory address 4 is executed. It is also an load word instruction which loads the value of memory address 132 to register $s1. Then an add instruction follows which adds the two operands written into the registers $s and $s1 and writes the result to register $s2. Then a store word instruction writes the content of register $s2 to the memory at address 136. The following instructions are for subtract, add, or, slt, beq and jump. The result of a computation is always stored to the memory by a store word instruction. Note For description of the register numbers and names used for the test see Figure 3.13 of [PaHe98] p. 14. The used assembler instructions are not completely declared in this report. For information on the machine language see [PaHe98] Chapter 3, especially figure 3.14 on page M. Linder, M. Schmid, 7/7

59 6.2 Simulation Result 6.2 Simulation Result Figure 6.1 Simulation Results of MIPS and Memory M. Linder, M. Schmid, 7/7 49

60 7 Conclusion 7 Conclusion 7.1 Our own experiences While working on our miniproject, we applied a lot of knowledge learned in the lecture VHDL. Furthermore, we gained a lot of experience in using the simulation and synthesis tools. It was very interesting and exciting to describe real hardware and to see the expected results in simulation and the block diagrams after synthesis. Our miniproject implementing a processor in VHDL has been a real challenge. The complexity was not located in the single components, but rather in the implementation of the synchronous operation of the whole control and datapath. Due to an intensive preparation of the desired hardware according to the literature Computer Organization & Design [PaHe98], we prevented unintended design errors. Since our project transcends a pure implementation of VHDL code, we were able to gain experience in hierarchical design with component instantiation and package design. Additionally, while implementing a microprocessor, we could refresh our knowledge in processor operations, memory addressing and MIPS instruction coding. 7.2 Annotations to Computer Organization & Design [PaHe98] Since the design of our MIPS processor is closely connected to the literature [PaHe98], we read the chapter 5 in detail. Overall, we adjusted the design as conform as possible to the description in [PaHe98]. There are some passages which do not provide a full description, e.g. the output signals of the control FSM are not listed completely for each state. Nevertheless, Computer Organization & Design by Patterson and Hennessy provides a brilliant composition describing the control and datapath of a processor implementation. 5 M. Linder, M. Schmid, 7/7

61 7.3 Further work on the project 7.3 Further work on the project Although we spent much more time than scheduled, we did not reach all our aims. For further work on the project, we recommend our successors to continue the following tasks Verify the synthesis results (with VHDL code created by Quartus) with desired behavior implemented in RTL and seen in testbench simulation in order to obtain the desired unregistered memory output mentioned in chapter 4.2. Realise an hardware implementation of processor and memory in order to verify the behavior of the desired hardware on the Cyclone II Development & Education Board, e.g. debug the memory data. Introduce the pipelining of instructions described in chapter 6 [PaHe98] to improve the performance of the MIPS processor. M. Linder, M. Schmid, 7/7 51

62 8 Appendix 8 Appendix 8.1 Design files Project Entities LIBRARY IEEE USE IEEE.std_logic_1164.ALL ENTITY ControlFSM IS PORT (clk, rst_n IN std_ulogic instr_31_26 IN std_ulogic_vector(5 downto ) RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond OUT std_ulogic ALUOp, ALUSrcB, PCSource OUT std_ulogic_vector(1 downto ) ) END ControlFSM VHDLSource 8.1 e_control_controlfsm.vhd LIBRARY IEEE USE IEEE.std_logic_1164.ALL ENTITY ALUControl IS PORT (instr_15_ IN std_ulogic_vector(15 downto ) ALUOp IN std_ulogic_vector(1 downto ) ALUopcode OUT std_ulogic_vector(2 downto ) ) END ALUControl VHDLSource 8.2 e_control_alucontrol.vhd LIBRARY IEEE USE IEEE.std_logic_1164.ALL ENTITY control IS PORT (clk, rst_n IN std_ulogic instr_31_26 IN std_ulogic_vector(5 downto ) instr_15_ IN std_ulogic_vector(15 downto ) zero IN std_ulogic ALUopcode OUT std_ulogic_vector(2 downto ) RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite OUT std_ulogic ALUSrcB, PCSource OUT std_ulogic_vector(1 downto ) PC_en OUT std_ulogic ) END control VHDLSource 8.3 e_control.vhd 52 M. Linder, M. Schmid, 7/7