State Elements. Register File Design and Memory Design. An unclocked state element. Latches and Flip-flops

Transcription

1 SE 67.0: Introduction to omputer Architecture State Elements egister File esign and Memory esign Unclocked vs. locked locks used in synchronous logic when shouln element that contains state be updated? cycle time Falling edge Presentation E Slides by Gojko Babić lock period ising edge 07//00 An unclocked state element The set-reset output depends on present inputs anlso on past inputs Latches and Flip-flops Output is equal to the stored value inside the element (don't need to ask for permission to look at the value) hange of state (value) is based on the clock Latches: whenever the inputs change, and the clock is asserted Flip-flop: state changes only on a clock edge (edge-triggered methodology) S A clocking methodology defines when signals can be reand written wouldn't want to rea signal at the same time it was being written

2 - Two inputs: the data value to be stored () the clock signal () indicating when to read & store Two outputs: the value of the internal state () and it's complement flip-flop Output changes only on the clock edge _ Our Implementation An edge triggered methodology Typical execution: read contents of some state elements, send values through some combinational logic write results to one or more state elements State element ombinational logic State element egister File The register file includes -bit registers, as it is needed for general purpose registers of MIPS architecture Figure B..7 num ber num ber egister file rite register rite data rite data data lock cycle This register file makes possible to simultaneously read from two registers and write into one register as it is appropriate for MIPS processor. g. babic Presentation E

3 egister File Functioning The given register file functions as follows: any value provided on -line number port makes that content of corresponding register is provided on -line data port any value provided on -line number port makes that content of corresponding register is provided on -line data port on the falling edge of write line, values thappear on -bit rite data porre written into the register with the number on -line rite register port. Note that requirements for set-up time (and hold time) also apply here. number number egister File esign: Part egister 0 egister egister n egister n n=3 M u x M u x data data Figure B.. number number egister file rite register rite data data data This is a design a level of register and complex multiplexer. rite g. babic Presentation E 9 g. babic Presentation E 0 rite egister number egister data egister File esign: rite Part 0 n-to- decoder n n n=3 egister 0 egister egister n egister n number number egister file rite register rite data This is a design a level of register and decoder. data data g. babic Presentation E Figure B..9 e are now going to design the MIPS register file a level of flip-flop, basic multiplexer and decoder. rite Introduction to Memory esign Main memory is built in one of two technologies: - Static andom Access Memory AM - ynamic andom Access Memory A memory is normally built using a number of memory chips. Memory chips have specific configurations given as a product of two number, e.g. K* - K addressable locations with bit in each location, i.e. width of read/write operations is bit 6K* - 6K addressable locations with bits in each location, i.e. width of read/write operations is bits Notice that two chips above accommodate identical number of bits (K bits). Both memories are volatile. g. babic Presentation E

4 and AM: Bit Memory ell In technology, a three-state - is the basic building block, i.e. basic memory cell. Internally, a - can have a state corresponding to 0 or. In AM technology, the basic memory cell is built around one capacitor coupled with one transistor. The value in the cell is stores a charge. A charge can not be stored indefinitely and AM chips must be periodically refreshed. Since charges can be kept for several msec, -% of time is used for refreshing. AM Technology haracteristics Since 97, the main memory is composed of semiconductor AM s (ynamic andom Access Memory). AM chip capacity had been growing at rate of about 4 times every three years, while lately growth slowed down to times every two years. urrently, maximum AM chip capacity is M bits with an access time in the range nsec an cycle time of about 0 nsec. Access time & cycle time are two measures of memory latency: access time the time between a read is requestend when the desired contenrrives, cycle time the minimum time between two memory requests. For AM technology cycle time is longer than access time. For technology access time and cycle time are identical. g. babic Presentation E 3 g. babic Presentation E 4 Growth of apacity per AM chip Prices of Six Generations of AMs Figure.3 g. babic Presentation E g. babic Presentation E 6

5 Technology haracteristics Static andom Access Memory technology is normally used for caches. In comparable technologies, cycle time is about to 6 times faster than AM, e.g. currently 0.- nsec. Since address lines are not multiplexed, there is no difference between access time and cycle time. But, chip capacity (as well as density) is roughly 4 to times less than that of AM Also is more expensive, e.g. GB in 004 $4,000 $0,000 for and $00 $00 for AM. In addition, chips have higher power consumption and power dissipation than AM chips. Thus designs are concerned with speed, while in AM designs the emphasis is on cost per bind capacity. g. babic Presentation E 7 Example: K chip reand write operations are bits wide there are K addressable locations Memory hip Functioning h ip s e l e c t enable rite enable i n [ 7 0 ] A M 3 K Functioning of memory chip: S(hip select) has to be set for either reading or writing ( enable)=0 & (rite enable)=0 chip is not being accessed =0 and = write values at in lines into the chip address at lines = and =0 read into out lines values from the chip address at lines = and = nollowed Two designs of memory chip: Basic structure design Typical organization design g. babic Presentation E o u t [ 7 0 ] Basic Structure esign of 4 hip hip select hip Select Output enable out[ 0] 4 in[] in[0] rite enable in[ 0] riteenable 0 -to-4 decoder 3 Figure B.9.3 esign of Memory hip Basic Structure The design of the basic structure of chip uses some ideas from the register file design e.g. the write parts in two designs are identical. The main differences are in read part design. In the memory chip with the usage of three-state - es a multiplexer is eliminated. E.g. for K* chip, a multiplexer with K inputs each input having lines would be needed. But for design of the basic structure of chip, we still nee very large decoder. E.g. for K* chip, a decoder with input lines (that is not so bad) and K output lines (that is bad) is required. Typical organization of uses two level decoding that eliminates need for that very large decoder. out[] out[0] g. babic Presentation E 9 g. babic Presentation E 0

6 4 Array of - Latches Typical Organization esign hip Select riteenable 0 -to-4 decoder E E The next example will be using 64 array of -es. in[] in[0] Example: esign (read part only) a typical organization (i.e. two level decoding design) of K chip that uses *64 arrays of - es. Note: Arrays used have to have a bit capacity equal to a number of addressable locations in the chip, e.g. in this example that condition is satisfied since *64 = K. A number of arrays used should be equal to the number of bits in each memory location. [ 4 6 ] 9-to- decoder 64 E [ 0] 3 E out[] out[0] g. babic out7 out6 out out4 out3 out out out0 AM memory chip would have similar design. g. babic Presentation E Main Memory Specification A memory has identical inputs and outputs as memory chips, except that S does not exist. But the specification of a memory should include: a. memory capacity (usually in bytes), b. memory addressability, i.e. smallest unit that has its address, d. width of read/write operations, i.e. a number of bits that can be read or written from/to memory. Operations on memory: reading from memory and writing into memory; =0 and E=0 memory is not being accesses =0 and E= writing into memory = and E=0 reading from memory = and E= nollowed Main Memory Specification: Example Provide inputs and outputs of MByte memory with -bit Note that -bit read/write operations requires byte addressability. in E M e m MB =M units M e m out g. babic Presentation E 3 g. babic Presentation E 4

7 Main Memory Specification: Example Provide inputs and outputs of MByte memory with -bit Main Memory Specification: Example 3 Provide inputs and outputs of MByte memory with -bit read/write operations and -biddressability. E M e m E M e m in d a MB =M units out in MB =M units d a out M e m M e m g. babic Presentation E g. babic Presentation E 6 Steps in Memory esign. determine inputs and outputs for a memory to be design and memory chips thare being used;. determine number of memory chips needed; 3. determine number of memory chips in each set; a number of ound/or in lines in the set should be identical to number of ound/or in lines in the memory; 4. determine number of sets;. allocate sufficient number of memory address lines to select each of sets: those are the most significanddress lines 6. allocate next set of memory address lines as inputs to all memory chip address lines; 7. If the number of bits in read/write operations equals the number of bits in addressability, then all memory address lines are used up in steps and 6.. hen condition in 7 is not satisfied go to slide 6 9. onnect in and out lines of memory and chips g. babic Presentation E Memory esign: Example esign MByte memory using M* chips, with -bit in E M e m MB =M units M e m out Number of chips needed: 4 Number of chips per set: Number of sets: 4 g. babic Presentation E in S M out

8 Memory esign: Example esign MByte memory using 64M*4 chips, with -bit Memory esign: Example 3 esign MByte memory using M* chips, with -bit S S E M e m 6 E M e m in 9 MB =M units M e m Number of chips needed: 6 Number of chips per set: Number of sets: out g. babic Presentation E 9 in 4 64M 4 4 out in MB =M units M e m Number of chips needed: Number of chips per set: Number of sets: out g. babic Presentation E 30 in M out Memory esign: Example 4 esign MByte memory using M* chips, with -bit read/write operations and -biddressability. in E M e m MB =M units M e m out Number of chips needed: 6 Number of chips per set: 4 Number of sets: 4 g. babic Presentation E 3 in 3 M S out Steps in Memory esign (continued) This is the second part of step 7 in Steps in Memory esign slide: when the number of bits in read/write operations is greater than the number of bits in addressability, then some lowest order memory address lines are not used if the width of read/write operations doubles that of addressability then the least significant memory line is unused, if the width of read/read operations is 4 times greater than the number of bits in addressability then the two least significant memory lines are unused, etc. Note, it doesn t make sense to have the width of read/write operations smaller than addressability. g. babic Presentation E

9 Memory esign: Example esign MByte memory using M* chips, with -bit read/write operations and -bit (byte) addressability. S E M e m 3 in d a MB =M units M e m out in M out Number of chips needed: 6 Number of chips per set: 4 Number of sets: 4 g. babic Presentation E 33