Memory Devices. Future?

Transcription

1 Memory evices Small: Register file (group of numbered registers) Medium: SRAM (Static Random Access Memory) Large: RAM (ynamic Random Access Memory) Future? 1

2 Processor: ata Path Components Instruction Fetch and ecode Registers ALU Memory

3 SRAM: Static Random Access Memory Address 21 Chip select Output enable Write enable SRAM 2M out[15 0] in[15 0] 16 3

4 SRAM read port: data out Large register files are impractical. Big MUX = significant gate delay. Large memories use a shared output line. No central gates/mux to choose output! 5

5 Wired ORs (don't try this at home/in the lab, kids) anger, Will Robinson! 6

6 (noninverting) tristate buffers In Out Control In Control Out 0 0 Z 1 0 Z (active high) 7

7 SRAM cell one option Tristate Buffer ata In Q Clock Latch C Q ata Out Enable 8

8 SRAM write port: ata in: in[1] in[1] in [1] in [0] Write enable Write C latch Enable Q C latch Enable Q 0 0 Address 2-to-4 C latch Q C latch Q Enable Enable Address select in [i] out [i] C latch Q Enable Address 2-to C latch Enable C latch Enable Q Q C latch Enable C latch Enable Q Q Write enable ata out: out[1] [1] out out[0]

9 Organization of a 16 x 4 SRAM (one option) 4-bit 4 to 16 data out 10

10 Selecting location bit to 16 data out 11

11 Another organization of a 16 x 4 SRAM Split-level row/column ing = physical multidimensional array! top (row) 2 bits 2 to 4 bottom 2 bits (column) Notice the smaller... how does this affect timing? 12

12 Selecting location 0010 Nibbles "striped" across 4 smaller memories. top (row) 2 bits to 4 10 bottom 2 bits (column) 13

13 Selecting location 1101 Nibbles "striped" across 4 smaller memories. (row) top 2 bits to 4 01 bottom 2 bits (column) 14

14 What value does location 1010 hold? to

15 Organization of a 4M x 8 SRAM (one option) = 4 MB memory, size of a large cache for modern laptop Address [21 10] 12 to K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM 4K 1024 SRAM Address [9 0] 1024 out7 out6 out5 out4 out3 out2 out1 out0 In practice, single set of data lines often time-shared for read (out)/write (in). 16

16 Word line Pass transistor Capacitor ynamic RAM = RAM RAM stores bit as charge on capacitor: 1 transistor accesses stored charge. requires periodic refresh = read-write (dynamic power) Bit line SRAM stores bit on pair of inverting gates: several transistors requires continuous (static) power. 17

17 RAM design (one option) Row 11-to array Address[10 0] Single set of lines, time-shared for row, column. Column latches Accesses entire row, stores in column latches. Mainly used for refreshing entire row at a time. Accessing other columns in same row again cheaper...? out 18

18 64-bit RAM 3 to 8 row 3-bit Column latches ata out 19

19 Reading bit at Select row 3 to 8 row bit Column latches ata out 20

20 Reading bit at Copy row to latches 3 to 8 row Row is fading! bit Column latches ata out 21

21 Reading bit at Refresh row from latches 3 to 8 row Refresh bit Column latches ata out 22

22 Reading bit at Select column from latches 3 to 8 row bit Column latches ata out 23