CprE 281: Digital Logic

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1 CprE 281: Digital Logic Instructor: Alexander Stoytchev

2 Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

3 Administrative Stuff HW3 is due on Monday Sep 4p

4 Administrative Stuff HW4 is out It is due on Monday Sep 4pm. Please write clearly on the first page (in BLOCK CAPITAL letters) the following three things: Your First and Last Name Your Student ID Number Your Lab Section Letter Also, please Staple your pages

5 Administrative Stuff TA Office Hours: 5:00 pm - 6:00 pm on Tuesdays (Vahid Sanei-Mehri) Location: 3125 Coover Hall 11:10 am-1:10 pm on Wednesdays (Siyuan Lu) Location: TLA (Coover Hall - first floor) 5:00 pm - 6:00 pm on Thursdays (Vahid Sanei-Mehri) Location: 3125 Coover Hall 10:00 am-12:00 pm on Fridays (Krishna Teja) Location: 3214 Coover Hall

6 Midterm Exam #1 Administrative Stuff When: Friday Sep 22. Where: This classroom What: Chapter 1 and Chapter 2 plus number systems The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes). More details to follow.

7 Quick Review

8 2-1 Multiplexer (Definition) Has two inputs: x 1 and x 2 Also has another input line s If s=0, then the output is equal to x 1 If s=1, then the output is equal to x 2

9 Graphical Symbol for a 2-1 Multiplexer s x 1 x f [ Figure 2.33c from the textbook ]

10 Let s Derive the SOP form s x 1 x 2 s x 1 x 2 s x 1 x 2 s x 1 x 2 f (s, x 1, x 2 ) = s x 1 x 2 + s x 1 x 2 + s x 1 x 2 + s x 1 x 2

11 Let s simplify this expression f (s, x 1, x 2 ) = s x 1 x 2 + s x 1 x 2 + s x 1 x 2 + s x 1 x 2 f (s, x 1, x 2 ) = s x 1 (x 2 + x 2 ) + s (x 1 +x 1 )x 2 f (s, x 1, x 2 ) = s x 1 + s x 2

12 Circuit for 2-1 Multiplexer x 1 s s x 2 f x 1 x f (b) Circuit (c) Graphical symbol f (s, x 1, x 2 ) = s x 1 + s x 2 [ Figure 2.33b-c from the textbook ]

13 Analogy: Railroad Switch

14 Analogy: Railroad Switch x 1 x 2 select f

15 Analogy: Railroad Switch x 1 x 2 select f This is not a perfect analogy because the trains can go in either direction, while the multiplexer would only allow them to go from top to bottom.

16 More Compact Truth-Table Representation s x 1 x 2 f (s, x 1, x 2 ) (a) Truth table s 0 1 f (s, x 1, x 2 ) x 1 x 2 [ Figure 2.33 from the textbook ]

17 4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3 We ll talk more about this when we get to chapter 4, but here is a quick preview.

18 Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

19 The long-form truth table [

20 4-1 Multiplexer (SOP circuit) [ Figure 4.2c from the textbook ]

21 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer s 1 s 0 w 0 w f w 2 w [ Figure 4.3 from the textbook ]

22 Analogy: Railroad Switches

23 Analogy: Railroad Switches w 0 w 1 w 2 w 3 s 1 f

24 Analogy: Railroad Switches w 0 w 1 w 2 w 3 s 0 these two switches are controlled together s 1 f

25 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

26 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer w 0 s 1 s 0 w 1 w 2 f w 3

27 That is different from the SOP form of the 4-1 multiplexer shown below, which uses fewer gates

28 16-1 Multiplexer s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 [ Figure 4.4 from the textbook ]

29 [

30 7-Segment Display Example

31 Display of numbers [ Figure 2.34 from the textbook ]

32 Display of numbers

33 Display of numbers a = s 0 c = s 1 e = s 0 g = s 1 s 0 b = 1 d = s 0 f = s 1 s 0

34 Intro to Verilog

35 Created in 1983/1984 History Verilog-95 (IEEE standard ) Verilog 2001 (IEEE Standard ) Verilog 2005 (IEEE Standard ) SystemVerilog SystemVerilog 2009 (IEEE Standard ).

36 HDL Hardware Description Language Verilog HDL VHDL

37 Verilog HDL!= VHDL These are two different Languages! Verilog is closer to C VHDL is closer to Ada

38 [ Figure 2.35 from the textbook ]

39 Hello World in Verilog [

40 The Three Basic Logic Gates x x x 1 x x 1 x 2 2 x 1 x x 1 + x 2 2 NOT gate AND gate OR gate You can build any circuit using only these three gates [ Figure 2.8 from the textbook ]

41 How to specify a NOT gate in Verilog x x NOT gate

42 How to specify a NOT gate in Verilog we ll use the letter y for the output x y NOT gate

43 How to specify a NOT gate in Verilog x y not (y, x) NOT gate Verilog code

44 How to specify an AND gate in Verilog x 1 f= x x 1 x 2 2 and (f, x1, x2) AND gate Verilog code

45 How to specify an OR gate in Verilog x 1 f= x x 1 + x 2 2 or (f, x1, x2) OR gate Verilog code

46 2-1 Multiplexer [ Figure 2.36 from the textbook ]

47 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.37 from the textbook ]

48 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.40 from the textbook ]

49 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.42 from the textbook ]

50 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.43 from the textbook ]

51 Another Example

52 Let s Write the Code for This Circuit [ Figure 2.39 from the textbook ]

53 Let s Write the Code for This Circuit module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; endmodule and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); [ Figure 2.39 from the textbook ] [ Figure 2.38 from the textbook ]

54 Let s Write the Code for This Circuit module example4 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; endmodule assign g = (x1 & x3) (x2 & x4); assign h = (x1 ~x3) & (~x2 x4); assign f = g h; [ Figure 2.39 from the textbook ] [ Figure 2.41 from the textbook ]

55 Yet Another Example

56 A logic circuit with two modules [ Figure 2.44 from the textbook ]

57 The adder module [ Figure 2.12 from the textbook ]

58 The adder module [ Figure 2.45 from the textbook ]

59 The display module a = s 0 c = s 1 e = s 0 g = s 1 s 0 b = 1 d = s 0 f = s 1 s 0

60 The display module a = s 0 b = 1 c = s 1 d = s 0 e = s 0 f = s 1 s 0 g = s 1 s 0 [ Figure 2.46 from the textbook ]

61 Putting it all together

62 Questions?

63 THE END

CprE 281: Digital Logic

CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev