CprE 281: Digital Logic


 Mark Mathews
 2 years ago
 Views:
Transcription
1 CprE 28: Digital Logic Instructor: Alexander Stoytchev
2 Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 Administrative Stuff HW4 is out It is due on Monday Sep 4 pm It is posted on the class web page I also sent you an with the link.
4 Example: KMap for the 2 Multiplexer
5 2 Multiplexer (Definition) Has two inputs: x and Also has another input line s If s=, then the output is equal to x If s=, then the output is equal to
6 Circuit for 2 Multiplexer x s s f x f (b) Circuit (c) Graphical symbol [ Figure 2.33bc from the textbook ]
7 Truth Table for a 2 Multiplexer [ Figure 2.33a from the textbook ]
8 [ Figure 2.33a from the textbook ] Let s Draw the Kmap
9 Let s Draw the Kmap
10 Let s Draw the Kmap
11 Let s Draw the Kmap
12 Let s Draw the Kmap
13 Let s Draw the Kmap f (s, x, ) = x + s x
14 Let s Draw the Kmap f (s, x, ) = x + s x Something is wrong!
15 Compare this with the SOP derivation
16 Let s Derive the SOP form
17 Let s Derive the SOP form
18 Let s Derive the SOP form Where should we put the negation signs? s x s x s x s x
19 Let s Derive the SOP form s x s x s x s x
20 Let s Derive the SOP form s x s x s x s x f (s, x, ) = s x + s x + s x + s x
21 Let s simplify this expression f (s, x, ) = s x + s x + s x + s x
22 Let s simplify this expression f (s, x, ) = s x + s x + s x + s x f (s, x, ) = s x ( + ) + s (x +x )
23 Let s simplify this expression f (s, x, ) = s x + s x + s x + s x f (s, x, ) = s x ( + ) + s (x +x ) f (s, x, ) = s x + s
24 Let s Draw the Kmap again [ Figure 2.33a from the textbook ]
25 Let s Draw the Kmap again
26 Let s Draw the Kmap again
27 Let s Draw the Kmap again
28 Let s Draw the Kmap again s x The order of the labeling matters.
29 Let s Draw the Kmap again s x
30 Let s Draw the Kmap again s x
31 Let s Draw the Kmap again s x
32 Let s Draw the Kmap again s x f (s, x, ) = s x + s This is correct!
33 Two Different Ways to Draw the Kmap x x 3 m x x 3 m m 2 m m 2 m 6 m 4 m 3 m 4 m m 3 m 7 m 5 m 5 (b) Karnaugh map m 6 m 7 x 3 x (a) Truth table m m m 3 m 2 m 4 m 5 m 7 m 6
34 Another Way to Draw 3variable Kmap x x 3 m m m 2 m 3 m 4 m 5 m 6 m 7 x x 3 m m m 3 m 2 m 6 m 7 (b) Karnaugh map x x 3 m 4 m 5 (a) Truth table m m 4 m m 5 m 3 m 7 m 2 m 6
35 Gray Code Sequence of binary codes Consecutive lines vary by only bit
36 Gray Code & Kmap s x
37 Gray Code & Kmap s x
38 Gray Code & Kmap s x These two neighbors differ only in the LAST bit
39 Gray Code & Kmap s x These two neighbors differ only in the LAST bit
40 Gray Code & Kmap s x These two neighbors differ only in the FIRST bit
41 Gray Code & Kmap s x These two neighbors differ only in the FIRST bit
42 Adjacency Rules s x adjacent columns
43 Gray Code & Kmap s x These four neighbors differ in the FIRST and LAST bit They are similar in their MIDDLE bit
44 A fourvariable Karnaugh map x x x 3 x 4 m m 4 m 2 m 8 m m 5 m 3 m 9 x 3 m 3 m 2 m 6 m 7 m 5 m 4 m m x 4 [ Figure 2.53 from the textbook ]
45 A fourvariable Karnaugh map x x2 x3 x4 m m m2 m3 m4 m5 m6 m7 m8 m9 m m m2 m3 m4 m5 x x 3 x 4 x 3 m m m 5 m 3 m 2 m 6 m 4 m 2 m 3 m 7 m 5 m 4 x m 8 m 9 m m x 4
46 Adjacency Rules adjacent rows adjacent columns adjacent columns
47 Gray Code & Kmap x x2 x3 x4 m m m2 m3 m4 m5 m6 m7 m8 m9 m m m2 m3 m4 m5 x x 3 x 4 x 3 m m m 5 m 3 m 2 m 6 m 4 m 2 m 3 m 7 m 5 m 4 x m 8 m 9 m m x 4
48 Gray Code & Kmap x x2 x3 x4 m m m2 m3 m4 m5 m6 m7 m8 m9 m m m2 m3 m4 m5 x x 3 x 4 x 3 m m m 5 m 3 m 2 m 6 m 4 m 2 m 3 m 7 m 5 m 4 x m 8 m 9 m m x 4
49 Example of a fourvariable Karnaugh map [ Figure 2.54 from the textbook ]
50 Example of a fourvariable Karnaugh map [ Figure 2.54 from the textbook ]
51 Strategy For Minimization
52 Grouping Rules Group s with rectangles Both sides a power of 2: x, x2, 2x, 2x2, x4, 4x, 2x4, 4x2, 4x4 Can use the same minterm more than once Can wrap around the edges of the map Some rules in selecting groups: Try to use as few groups as possible to cover all s. For each group, try to make it as large as you can (i.e., if you can use a 2x2, don t use a 2x even if that is enough).
53 Terminology Literal: a variable, complemented or uncomplemented Some Examples: _ X X 2
54 Terminology Implicant: product term that indicates the input combinations for which function output is Example _ x  indicates that x and x yield output of _ x
55 Terminology Prime Implicant Implicant that cannot be combined into another implicant with fewer literals Some Examples x x x 3 x 3 Not prime Prime
56 Terminology Essential Prime Implicant Prime implicant that includes a minterm not covered by any other prime implicant Some Examples x 3 x
57 Terminology Cover Collection of implicants that account for all possible input valuations where output is Ex. Ex. x x 3 + x x 3 + x x 3 x x 3 + x x 3 x x 3
58 Give the Number of Implicants? Prime Implicants? Example Essential Prime Implicants? x x 3
59 Why concerned with minimization? Simplified function Reduce the cost of the circuit Cost: Gates + Inputs Transistors
60 Threevariable function f (x,, x 3 ) = Σ m(,, 2, 3, 7) x 3 x x x 3 [ Figure 2.56 from the textbook ]
61 Example x x 3 x 4
62 Example x x 3 x 4
63 Example x x 3 x 4 x x 3 x 4 x 3 x 4 x x 3 x 4 x 3 x 4
64 Example: Another Solution x x 3 x 4 x x 3 x 4 x 3 x 4 x x 3 x 4 x 3 x 4 x x 4 x x 4 x x 3 x x 3 [ Figure 2.59 from the textbook ]
65 f ( x,, x 4 ) = Σ m(2, 3, 5, 6, 7,,, 3, 4) x x 3 x 4 x x 4 x 3 x 4 x 3 x 4 x x 3 x 3 [ Figure 2.57 from the textbook ]
66 x f ( x,, x 4 ) = Σ m(, 4, 8,,, 2, 3, 5) x 3 x 4 x 3 x 4 x x 3 x x 4 x x 3 x 4 x x 3 x x 4 [ Figure 2.58 from the textbook ]
67 Minimization of ProductofSums Forms
68 Do You Still Remember This Boolean Algebra Theorem?
69 Let s prove 4.b
70 Let s prove 4.b
71 Let s prove 4.b
72 Let s prove 4.b
73 Let s prove 4.b
74 Let s prove 4.b They are equal.
75 Grouping Example x x 2 x M M 2
76 Grouping Example x x 2 x x * = M * M 2 = M * M 2
77 Grouping Example x x 2 x x * = M * M 2 = M * M 2
78 Grouping Example x x 2 x x * = M * M 2 = M * M 2
79 Grouping Example x x 2 x x * = M * M 2 = M * M 2 _ ( x + ) * ( x + ) = Property 4b (Combining)
80 POS minimization of f (x,, x 3 ) = Π M(4, 5, 6) x 3 x ( x + x 3 ) ( x + ) [ Figure 2.6 from the textbook ]
81 POS minimization of f ( x,, x 4 ) = Π M(,, 4, 8, 9, 2, 5) x x 3 x 4 ( x 3 + x 4 ) ( + x 3 ) ( x + + x 3 + x 4 ) [ Figure 2.6 from the textbook ]
82 Questions?
83 THE END
Chapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationCombinational Logic Circuits Part III Theoretical Foundations
Combinational Logic Circuits Part III Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationPoints Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions SumofProducts (SOP),
More informationKarnaugh Map (KMap) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using Kmap
Karnaugh Map (KMap) Ch. 2.4 Ch. 2.5 Simplification using Kmap A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8 Terminology For
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationDigital Circuits ECS 371
Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 7 Office Hours: KD 367 Monday 9::3, :33:3 Tuesday :3:3 Announcement HW2 posted on the course web site Chapter 4: Write down
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Twolevel Optimization Manipulating a function until it is
More informationEEE130 Digital Electronics I Lecture #4_1
EEE130 Digital Electronics I Lecture #4_1  Boolean Algebra and Logic Simplification  By Dr. Shahrel A. Suandi 46 Standard Forms of Boolean Expressions There are two standard forms: Sumofproducts form
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More information9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A
University of Illinois at UrbanaChampaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a
More informationHomework. Update on website issue Reading: Chapter 7 Homework: All exercises at end of Chapter 7 Due 9/26
Homework Update on website issue Reading: hapter 7 Homework: All exercises at end of hapter 7 Due 9/26 opyright c 22 28 UMaine omputer Science Department / 2 OS 4: Foundations of omputer Science Karnaugh
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More informationOptimized Implementation of Logic Functions
June 25, 22 9:7 vra235_ch4 Sheet number Page number 49 black chapter 4 Optimized Implementation of Logic Functions 4. Nc3xe4, Nb8 d7 49 June 25, 22 9:7 vra235_ch4 Sheet number 2 Page number 5 black 5 CHAPTER
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationece5745planotes.txt
ece5745planotes.txt ========================================================================== Follow up on PAL/PROM/PLA Activity ==========================================================================
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationOutcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps
.. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 2 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh Maps Overview Kmaps: an alternate approach to representing oolean functions Kmap representation can be used to
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationDIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (KMAPS)
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (KMAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function
More informationENGIN 112. Intro to Electrical and Computer Engineering
ENIN 2 Intro to Electrical and Computer Engineering Lecture 6 More Boolean Algebra ENIN2 L6: More Boolean Algebra September 5, 23 A B Overview Epressing Boolean functions Relationships between algebraic
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationAnnouncements. Chapter 2  Part 1 1
Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationLecture 22: Implementing Combinational Logic
8 Lecture 22: Implementing ombinational Logic S 5 L22 James. Hoe Dept of EE, MU April 9, 25 Today s Goal: Design some combinational logic circuits Announcements: Read Rizzoni 2.4 and 2.5 HW 8 due today
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 04 Boolean Expression Simplification and Implementation OBJECTIVES: To understand the utilization
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationTo write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.
3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More information(Refer Slide Time 6:48)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture  8 Karnaugh Map Minimization using Maxterms We have been taking about
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationPOWR IP PZ1/17
Silesian University of Technology as Centre of Modern Education Based on Research and Innovations POWR.03.05.00IP.0800PZ1/17 Project cofinanced by the European Union under the European Social Fund
More informationPresented By : Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak
Presented By : Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak Content  Introduction 2 Feature 3 Feature of BJT 4 TTL 5 MOS 6 CMOS 7 K Map  Introduction Logic IC ASIC: Application Specific
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More information2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. KMaps Can Identify SingleGate Functions
University of Illinois at UrbanaChampaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing TwoLevel Logic SOP Form Gives Good Performance s you know, one can use a Kmap
More informationKarnaugh Maps. Kiril Solovey. TelAviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22
Karnaugh Maps Kiril Solovey TelAviv University, Israel April 8, 2013 Kiril Solovey (TAU) Karnaugh Maps April 8, 2013 1 / 22 Reminder: Canonical Representation Sum of Products Function described for the
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Floating Point Numbers CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationDepartment of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic
Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying
More informationA graphical method of simplifying logic
45 Karnaugh Map Method A graphical method of simplifying logic equations or truth tables. Also called a K map. Theoretically can be used for any number of input variables, but practically limited to 5
More informationSimplification of twolevel combinational logic
ombinational logic optimization! lternate representations of oolean functions " cubes " karnaugh maps! Simplification " twolevel simplification " exploiting don t cares " algorithm for simplification
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flipflops Functional bocks: Combinational, Sequential Instruction
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design JieHong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps Kmap Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/kmapswalksandgraycodes/
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Binary Numbers CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More information4 KARNAUGH MAP MINIMIZATION
4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationStandard Boolean Forms
Standard Boolean Forms In this section, we develop the idea of standard forms of Boolean expressions. In part, these forms are based on some standard Boolean simplification rules. Standard forms are either
More informationEECS 140/141 Introduction to Digital Logic Design Fall Semester 2016 Exam #1 Date: 3 October 2016
EECS 4/4 Introduction to Digital Logic Design Fall Semester 26 Exam # Date: 3 October 26 NAME: KUID: General Instructions. This exam is closedbook. You are allowed a noncommunicating calculator and one
More informationObjectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure
Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:
More informationLast Name Student Number. Last Name Student Number
University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Midterm Examination ECE 241F  Digital Systems Wednesday October 13, 2004, 6:00pm [5]
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationChap2 Boolean Algebra
Chap2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital
More informationMenu. Algebraic Simplification  Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification
Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification  Boolean Algebra Minterms (written as m i ):
More informationSwitching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION
Switching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION Twovariable kmap: A twovariable kmap can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,
More informationEECS 140/141 Introduction to Digital Logic Design Spring Semester 2017 Exam #1 Date: 27 February 2017
EECS 4/4 Introduction to Digital Logic Design Spring Semester 27 Exam # Date: 27 February 27 NAME: KUID: General Instructions. This exam is closedbook. You are allowed a noncommunicating calculator and
More informationAustin Herring Recitation 002 ECE 200 Project December 4, 2013
1. Fastest Circuit a. How Design Was Obtained The first step of creating the design was to derive the expressions for S and C out from the given truth tables. This was done using Karnaugh maps. The Karnaugh
More informationSEE1223: Digital Electronics
SEE223: Digital Electronics 3 Combinational Logic Design Zulkifil Md Yusof Dept. of Microelectronics and Computer Engineering The aculty of Electrical Engineering Universiti Teknologi Malaysia Karnaugh
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More information