Altera/Synopsys User Guide

Transcription

1 Altera/Synopsys User Guide

2 About this User Guide July 1995 This user guide provides design guidelines, sample VHDL designs, Altera-specific design methods, and optimal synthesis options to assist designers using Synopsys synthesis tools to process designs targeted for Altera high-capacity programmable logic devices (HCPLDs). Using this information, designers can optimize designs processed in Synopsys and MAX+PLUS II for increased performance and device utilization. For complete information on Altera HCPLDs, refer to the Altera 1995 Data Book. For information on MAX+PLUS II, refer to MAX+PLUS II Help. For information on installing the Altera/Synopsys Design Kit, or configuring the Synopsys tools to process designs for Altera HCPLDs, please refer to Altera s Application Note 34 (Synopsys & MAX+PLUS II Logic Design). For immediate assistance on technical questions, call: Altera Applications Hotline (800) 800-EPLD For information on product availability, pricing, and order status, contact your local Altera representative or distributor listed in Sales Offices, Distributors & Representatives in this user guide. If you have questions that cannot be answered by the your local representative or distributor, contact: Altera Customer Marketing TEL : (408) FAX: (408) Altera Corporation iii

3 Contents July 1995 Introduction Overview...1 Prerequisites...3 Design Tools...3 Preview...3 Design Flow Summary...5 Introduction...5 Design Synthesis...7 Simulation...8 Getting Started with Design Compiler...8 Getting Started with MAX+PLUS II...10 Design Example...14 VHDL Coding Techniques Summary...21 Introduction...21 Generic Synthesis Strategies...21 Altera-Specific Synthesis Strategies...22 Instantiation vs. Inference...23 Basic Building Blocks...24 State Machine Design...35 Design Pipelining...39 Available Reference Libraries...43 Altera-Supplied Macrofunctions...44 DesignWare...48 Logic Synthesis Options Summary...53 Basic Strategy...53 Synopsys Optimization...54 Passing Data to MAX+PLUS II...58 MAX+PLUS II Optimization...60 Passing Data Back to Synopsys...62 Altera Corporation v

4 Contents Appendix A: Voic Sample File vi Altera Corporation

5 Introduction July 1995 Overview Programmable logic devices (PLDs) have historically been ideal prototyping vehicles to evaluate custom-silicon designs, and this application for Altera s devices continues to grow in importance. With the advent of devices with densities up to 100,000 gates, high-capacity PLDs (HCPLDs) are now candidates to replace gate arrays. Altera s MAX+PLUS II development system supports HCPLD development, and has been enhanced to meet the requirements of those designers who wish to use HCPLDs for gate array prototyping and replacement. Altera recognizes that most custom-silicon development projects now use industry-standard EDA design entry, synthesis and simulation tools, and Altera is committed to fitting seamlessly into the gate array design process. One of the more popular EDA synthesis and simulation packages is available from Synopsys. The Synopsys Design Compiler and FPGA Compiler provide advanced logic synthesis capabilities, and the VHDL System Simulator (VSS) provides a simulation tool for pre- and postsynthesis design evaluation. Although the Synopsys tools are used primarily for gate array development projects, Synopsys has also kept pace with the developments in programmable logic, and has worked closely with Altera to improve the links between MAX+PLUS II and Synopsys design tools. The result of this cooperative effort is the Altera/Synopsys interface. Figure 1 shows the Altera/Synopsys design flow. Designs synthesized by Synopsys are described in VHDL or Verilog HDL. The movement to hardware description language (HDL) description of logic circuits is accelerating as device gate-density passes the point where a graphical representation of a circuit design is practical. If an HCPLD is the final target, the HDL can be technology-specific and may use Alterasupplied optimized macrofunctions. For designs that will be retargeted, the HDL is generally technology-independent, and uses the DesignWare behavioral operators and standard VHDL operations and constructs. Altera Corporation 1

6 Introduction Figure 1. Altera/Synopsys Design Flow Overview VHDL Design Altera Synthesis & Technology Libraries Verilog HDL Design Design Compiler or FPGA Compiler EDIF Netlist MAX+PLUS II Compiler VHDL System Simulator (VSS) The HDL design is synthesized by the Synopsys FPGA Compiler or Synopsys Design Compiler using Altera-supplied synthesis libraries, and exported as an EDIF file. The FPGA Compiler and Design Compiler yield similar results but have different interfaces. This document refers to the Design Compiler. The EDIF netlist exported by the Design Compiler is expressed in terms of the elements in the Altera synthetic libraries, and is optimized for the target architecture. MAX+PLUS II imports the EDIF file and resynthesizes the netlist for a second-pass synthesis to finalize the fitting into the target device. If the design does not fit into a single Altera device, MAX+PLUS II automatically partitions the design across multiple devices, which dramatically enhances designer efficiency by eliminating the need to manually partition the original HDL design. The design can be simulated at any time during the design process. The Synopsys-supplied VHDL System Simulator (VSS) can evaluate the design before Synopsys synthesis, after Synopsys synthesis, and after MAX+PLUS II synthesis. Each type of simulation can use the same VHDL testbench, providing a high level of assurance that the logic synthesis has not changed the functionality of the original design. All designs in this document were compiled for an EPF8282 device with a generic speed grade. 2 Altera Corporation

7 Introduction Prerequisites This user guide assumes familiarity with the following topics: Digital design practices VHDL or Verilog HDL HDL simulation tools Basic Synopsys synthesis strategies Basic programmable logic device architecture Design Tools The sample files in this document were compiled and tested using the following design tools: Synopsys Design Compiler version 3.2 Synopsys VHDL System Simulator version 3.2 Altera MAX+PLUS II version 5.2 Preview Design Flow provides a detailed discussion of the Altera/Synopsys interface, as well as the file formats and design flows for the Synopsys Design Compiler and MAX+PLUS II. Design Flow also includes an annotated design example that shows how VHDL coding style and synthesis options can affect performance and fitting results. VHDL Coding Techniques discusses VHDL coding style and shows how to use the DesignWare and instantiation capabilities of VHDL to craft optimal source designs for Altera HCPLDs. VHDL Coding Techniques contains detailed instructions on how to implement specific functions or take advantage of the target device s architectural features at the sourcecode level. Logic Synthesis Options provides information on the impact of different logic synthesis options, and the best settings to use for different target architectures. Logic Synthesis Options discusses the settings for the Synopsys tools and the MAX+PLUS II software, and explains how the Synopsys synthesis tools and MAX+PLUS II work together. Altera recommends that you read this section before processing a design. Voic Sample File provides the VHDL source code for the voic sample file in this user guide. Altera Corporation 3

8 Notes:

9 Design Flow July 1995 Summary Introduction This section provides a detailed discussion of the Altera/Synopsys interface and describes the file formats and design flows available using Synopsys Synthesis tools and MAX+PLUS II. This section also includes an annotated design example that shows how VHDL coding style and synthesis options affect fitting results. The Synopsys Design Compiler or Synopsys FPGA Compiler can be used with MAX+PLUS II to create an integrated programmable logic design environment. The Altera/Synopsys design environment supports: Architecture-independent design entry for all Altera device families Links from MAX+PLUS II to Synopsys Design Compiler Back-annotation of timing values for Synopsys VHDL System Simulator (VSS) Enhanced area and timing prediction in Synopsys tools via delay and area models for Altera devices Short design cycles provided by the MAX+PLUS II software s automatic device selection, fitting, and multi-device partitioning The Altera/Synopsys design flow allows you to work with Synopsys as part of your normal design methodology, and then use MAX+PLUS II to implement the Altera technology portions of the design process, such as pin selection and device-specific optimization. The style and techniques covered in this user guide apply in general to VHDL and Verilog HDL, and to the Synopsys Design Compiler and FPGA Compiler. This user guide concentrates on targeting FLEX 8000 devices through VHDL and the Design Compiler. The complete Altera/Synopsys Design Flow is shown in Figure 1. Many features in the Synopsys Design Compiler and the Altera MAX+PLUS II design environment are not covered here. For more information, refer to Application Note 34 (Synopsys & MAX+PLUS II Logic Design). Altera Corporation 5

10 Design Flow Figure 2. Altera/Synopsys Design Flow Design Entry Verilog.v Verilog HDL Design File VHDL Design File HDL Compiler for Verilog Altera Synthesis & Technology Libraries.ADF.ADF or.sldb or.smf.smf.db Design Compiler FPGA Compiler VHDL AHDL or VHDL.vhd.tdf.vhd Text or VHDL Design File VHDL Compiler Altera Symbol Libraries.ADF.ADF or.sdb or.smf.smf Design Analyzer Standard Delay Format File & dc_shell Script File Design Processing syn2acf.sdf.dc EDIF Input File Message Text File MAX+PLUS II Message Processor.mtf Includes EDIF Netlist Reader & EDIF/Verilog/VHDL Netlist Writers MAX+PLUS II Compiler Library Mapping File(s).edf.lmf.lmf.ADF.ADF or or.smf.smf Programming Files.pof.jed.sof VHDL Output File.vho VHDL Design File.vhd EDIF Output File.edo Verilog Output File.vo Verilog HDL Design File.v Additional Output Files (e.g.,.snf,.fit,.rpt,.cnf,.sbf,.hex &.ttf files) Design Simulation Altera Functional Simulation Libraries Altera Functional Simulation Libraries Device Programming.ADF.ADF or.sim or.smf.smf.adf.adf or.vp or.smf.smf Altera Programming Software & Hardware Other Programming Software & Hardware VHDL Simulation Software VHDL System Simulator (VSS) EDIF Simulation Software Verilog Simulation Software 6 Altera Corporation

11 Design Flow 1 MAX+PLUS II also accepts VHDL directly and synthesizes it into gates. The acceptable input content differs from the Synopsys design style, and is not covered in this manual. For information on MAX+PLUS II support for VHDL Design Files (.vhd), refer to MAX+PLUS II Help. Design Synthesis This user guide describes the design flow for using the MAX+PLUS II Compiler to synthesize and fit an EDIF netlist file (either EDIF or 3 0 0) produced by the Synopsys Design Compiler, as shown in Figure 2. Flow Description The design flow for the Altera/Synopsys interface is described below: 1. Create a design in VHDL or in Verilog HDL. The design can be technology-independent or created with Altera-specific functions. For information on incorporating primitives and VHDL macrofunctions into your design, see Altera-Supplied Macrofunctions on page 44 in this user guide. 1 Altera recommends that you simulate your register transfer level (RTL) designs to verify correct operation before synthesis. 2. Import the design into either the Synopsys dc_shell or Design Analyzer. Depending on the language in which the design was entered, the VHDL Compiler for VHDL or the HDL Compiler for Verilog HDL automatically compiles the design as it is being read and translates it into Synopsys database format (.db). For more detailed information, refer to the Synopsys Design Compiler Reference Manual or Design Analyzer Reference Manual. 3. Synthesize the design using the appropriate technology and synthesus libraries to optimize the design for the target Altera device family. For more information on specifying libraries, see Altera s Application Note 34 (Synopsys & MAX+PLUS II Logic Design). a. (Optional) Verify design functionality prior to processing with MAX+PLUS II. To verify your design, save it from within the Design Compiler as a VHDL netlist file. Then use VSS and the VHDL simulation models in the alt_pre directory to simulate your design. b. (Optional) View the synthesized design with the Synopsys Design Analyzer. The Design Analyzer uses the altera.sdb symbol library to display synthesized schematics of the designs generated by the Design Compiler or FPGA Compiler. Altera Corporation 7

12 Design Flow 4. Save the synthesized design as an EDIF netlist file with the extension.edf so that MAX+PLUS II will recognize it as an EDIF Input File. 5. Start MAX+PLUS II, and compile the EDIF Input File. See Getting Started with MAX+PLUS II on page 10 of this user guide for more information on setting MAX+PLUS II options. The MAX+PLUS II Compiler generates all the files necessary to program Altera devices. In addition, the Compiler can generate a VHDL Output File (.vho), a Verilog Output File (.vo), and an EDIF Output File (.edo) for simulation with standard EDA tools. 1 Altera recommends that you perform a timing analysis of your design with the MAX+PLUS II Timing Analyzer to obtain postsynthesis timing information. Obtain area information about your design by consulting the Report File (.rpt) generated by MAX+PLUS II. Altera also recommends that you use a standard HDL simulator to perform full timing simulation of the EDIF Output File, VHDL Output File, or Verilog Output File generated by MAX+PLUS II. 6. Program an Altera HCPLD either with Altera programming hardware, or with programming hardware and software available from another manufacturer, such as Data I/O. For information on configuring SRAM-based FLEX 8000 devices, see Application Note 33 (Configuring FLEX 8000 Devices) and Application Note 38 (Configuring Multiple FLEX 8000 Devices). Simulation Getting Started with Design Compiler Although not specifically covered in this user guide, Altera recommends that you simulate your design in stages as you develop your HCPLD. Ideally, you should simulate at each stage of the development process using the same VHDL or Verilog HDL testbench or other stimulus method, and compare results of the more detailed implementations with earlier (more abstract) design results. This methodology allows you to develop a specification that can be simulated early in the process, when experimentation is relatively easy. Subsequently, more complex simulations serve as verification that the design specification has been met. This user guide assumes that you are using the Synopsys Design Compiler. You can also use the Synopsys FPGA Compiler with similar methods and results. The Synopsys Design Analyzer adds a graphical front end to the Design Compiler. Using the Design Analyzer is a good way to learn about the Synopsys software and to generate your first dc_shell scripts. The Design Analyzer is also useful for inspecting the preoptimized or post-optimized schematics generated by the Design Compiler. 8 Altera Corporation

13 Design Flow Design Compiler Start-Up File The.synopsys_dc.setup configuration file specifies the Altera technology you will use, whether you are using DesignWare, and the information required to generate correct EDIF netlists for MAX+PLUS II. This file must be set up correctly. Altera recommends that you use only a single.synopsys_dc.setup startup file, located in your home directory, to avoid confusion about the search path. The Synopsys Design Compiler looks for start-up files in the following locations, in the following order: 1. $SYNOPSYS/.synopsys_dc.setup 2. ~/.synopsys_dc.setup 3../.synopsys_dc.setup Directives found in a later file override files found earlier. Using dc_shell Scripts While it is possible to run Design Compiler or Design Analyzer by providing all commands interactively, you will most likely build a dc_shell script for your project that runs your synthesis process in a batch mode. As a minimum, a dc_shell script must include the following: read -f vhdl <design name>.vhd compile write -f edif -output <design name>.edf 1 The design name must be exactly the same as the top-level module of your synthesized design. Otherwise, MAX+PLUS II cannot process the design properly. Documentation The Synopsys Design Compiler on-line help is useful, and has an excellent search facility. As in MAX+PLUS II Help, you can copy and paste source code from sample files directly into your files. To open the Design Compiler on-line help, type: $SYNOPSYS/iview/bin/iview 9 Altera Corporation 9

14 Design Flow 1 Application Note 34 (Synopsys & MAX+PLUS II Logic Design) contains detailed and up-to-date information on how to set up the Altera/Synopsys interface. You should read this document before beginning a project that uses Synopsys to process designs for an Altera device. Getting Started with MAX+PLUS II This section provides the minimum information necessary to correctly configure MAX+PLUS II to process designs that are generated by the Synopsys Design Compiler or FPGA Compiler. In addition, MAX+PLUS II Help provides the most up-to-date software documentation. The MAX+PLUS II Compiler imports an EDIF Input File that is generated by Synopsys, synthesizes the design for a particular target technology and device, and generates simulation and device programming files. UNIX-based installations of MAX+PLUS II can be used in either an interactive or a command-line mode. You must use the interactive mode the first time you compile the design to set the project options and parameters. The graphical mode writes the Assignment & Configuration File (.acf) file, which contains all configuration information for a MAX+PLUS II compilation. Thereafter you can use the command-line mode. Interactive Mode To start MAX+PLUS II in interactive mode on a UNIX-based system, type the following command at the UNIX prompt: maxplus2 9 1 You can transfer the files generated by Synopsys to a Microsoft Windows-based version of MAX+PLUS II to complete the design cycle. To start MAX+PLUS II in interactive mode in a Windows environment, double-click on the MAX+PLUS II icon in the Program Manager. In addition, make sure the design file(s) comply with DOS filename conventions. Command-Line Mode MAX+PLUS II for workstations allows you to compile your designs in a batch mode from the UNIX command line. Before running MAX+PLUS II in command-line mode, you must first set the Compiler options in interactive mode. 10 Altera Corporation

15 Design Flow In command-line mode, warning and error messages are directed to std_out. To compile a design with MAX+PLUS II using the options set up in the project ACF, type: maxplus2 -c <project name> 9 Setting Compilation Options (Interactive Mode) After starting MAX+PLUS II in interactive mode, specify the following Compiler option settings before compiling your project: To specify the top-level EDIF Input File as the project to be compiled, choose Project Name (File menu), then type or choose the desired filename with the extension.edf. The filename must have a.edf extension to be imported into MAX+PLUS II. Choose OK. With the Compiler window open, choose EDIF Netlist Reader Settings (Interfaces menu). Choose Synopsys in the Vendor dropdown list box. Choose OK. (Optional) If DesignWare was used when Synopsys processed the design, ensure that the global project logic synthesis style uses the Manual setting for the Carry Chain and Cascade Chain logic options. To check and/or edit the global project synthesis style: a. Choose Global Project Logic Synthesis (Assign menu). b. Choose Define Synthesis Style. c. Select Manual in the Carry Chain box. d. Select Manual in the Cascade Chain box. e. Choose OK. Altera Corporation 11

16 Design Flow Set the desired options for: Logic synthesis Report File generation Programming file generation Simulation file generation Simulator Netlist File (.snf) generation Select one or more target device(s) for the project. If you do not specify a device, the MAX+PLUS II Compiler automatically selects one or more devices from the current device family. For automatic device selection, choose Device (Assign menu). Choose a device family, e.g., FLEX 8000, in the Device Family drop-down list box and choose AUTO in the Devices box. Choose OK. You can also specify the range of target devices by choosing Auto Device to open the Auto Device Selection dialog box. For manual device selection, choose Device (Assign menu). Choose a device family, e.g. FLEX 8000, in the Device Family drop-down list box, and choose a specific device, such as an EPF8282LC84, in the Devices box. Choose OK. You can assign all logic in the current project to a single device or to multiple devices. Go to MAX+PLUS II Help for a detailed description of how to partition designs into multiple devices. Generate output file(s) that contain timing information: To generate EDIF Output File(s), turn on the EDIF Netlist Writer command (Interfaces menu), then choose EDIF Netlist Writer Settings and choose Synopsys in the Vendor drop-down list box. Choose OK. To generate VHDL Output File(s), turn on the VHDL Netlist Writer command (Interfaces menu). To generate Verilog Output File(s), turn on the Verilog Netlist Writer command (Interfaces menu). Choose the Start button to compile the project. MAX+PLUS II imports the EDIF Input File, flattens the project, fits it into one or more Altera devices, and generates the selected output files, along with the files necessary for programming. The Message Processor window displays error, warning, and information messages. You can select a message and choose the Help on Message button to display information about the possible cause(s) and corrective action(s). The MAX+PLUS II Compiler also generates a Report File (.rpt) that shows how device resources are used in the project. 12 Altera Corporation

17 Design Flow If compilation is successful, the Compiler generates the appropriate programming file(s), a Fit File (.fit), a Simulator Netlist File (.snf), a Report File, and if specified, one or more Verilog Output Files, VHDL Output File(s), and EDIF Output File(s). Refer to Basic Tools in MAX+PLUS II Help for more information on MAX+PLUS II Compiler output files. MAX+PLUS II Timing Analyzer The MAX+PLUS II Timing Analyzer allows you to analyze the performance of a project after it has been synthesized by the Compiler. The Timing Analyzer offers three types of analysis: Delay Matrix for point-to-point timing information Setup/Hold Analysis for setup and hold time information Registered Performance for information on performance-limiting delays, minimum Clock period, and maximum Clock frequency f For more information on using the Timing Analyzer, go to MAX+PLUS II Timing Analyzer Help. MAX+PLUS II Floorplan Editor The MAX+PLUS II Floorplan Editor provides a graphical method for making the following assignments: Pins Logic cells The Floorplan Editor provides a drag-and-drop capability for assigning pin and logic cell locations, and provides a graphical view of current assignments as well as the locations used/assigned in the last successful compilation. You manually specify layout instructions using the Floorplan Editor, allow the Compiler to make the decisions for you, or use a mix of manual and automatic placement. For more information, consult MAX+PLUS II Floorplan Editor Help. Device Programming For information on device programming, see MAX+PLUS II Help. Altera Corporation 13

18 Design Flow PLD Architecture To obtain maximum performance from designs processed through Synopsys and MAX+PLUS II, you should be familiar with the target device architecture. This user guide provides some examples of how to take advantage of the FLEX 8000 device architecture. For detailed information on device architectures, refer to Altera s device family data sheets. Design Example The following section describes how the Altera/Synopsys design flow works. It is intended to illustrate the steps a designer would complete to process a design through the Synopsys Design Compiler and MAX+PLUS II. The sample design used in this section implements a voic controller. The complete VHDL file for the design is located in Voic Sample File. For a detailed illustration of the design flow, see Figure 2 on page 6. Directory Structure The.synopsys_dc.setup file is located in the home (~) directory. If this file is not set up properly or contains incorrect information, you may encounter problems when using the Altera/Synopsys interface. Set-up information is available in Design Environment in Application Note 34 (Synopsys & MAX+PLUS II Logic Design). Correct formatting of the.synopsys_dc.setup file insures that the reference libraries are visible and that all the Synopsys EDIF generation parameters are set correctly. Figure 3 shows a.synopsys_dc.setup file for the sample design. 14 Altera Corporation

19 Design Flow Figure 3. Design Compiler synopsys_dc.setup for Voic Project echo " " echo " Running ~kgi/.synopsys_dc.setup " echo " " designer = "kgi" company = "Altera" search_path = \ "/usr/maxplus2/synopsys/library/alt_syn/flex8000/lib \ $SYNOPSYS/libraries/syn" synthetic_library = "flex8000.sldb" link_library = "flex8000.sldb flex8000.db" target_library = "flex8000.db" symbol_library = "altera.sdb" define_design_lib DW_FLEX8000 -path /usr/maxplus2/synopsys/library/alt_syn/flex8000/lib/dw_flex8000 default_schematic_options = "-size infinite" hdlin_source_to_gates_mode = "low" edifout_netlist_only = "true"; edifout_power_and_ground_representation = "net"; edifout_power_net_name = "VDD"; edifout_ground_net_name = "GND"; edifout_no_array = "true"; edifin_power_net_name = "VDD"; edifin_ground_net_name = "GND"; Coding The top level of the design is a hand-coded structural interconnect of toplevel synthesizable modules. Each module was simulated and synthesized individually using the Synopsys Design Compiler. After each module was completed, the modules were interconnected and synthesized hierarchically. 1 The consistency of formatting in design coding is an important consideration, which should provide consistent comment formatting, indentation style, naming methodology, and identifier capitalization. Synopsys Synthesis The dc_shell script used for this project is shown in Figure 4. Altera Corporation 15

20 Design Flow Figure 4. Synopsys dc_shell Script for the Voic Project (Part 1 of 2) dc_shell <<! define_design_lib WORK -path /home/kgi/syn_work_lib read -f vhdl./vm_pak.p.vhd /* package, no designs */ read -f vhdl./decoder.vhd /* state machine example */ create_clock CLK -period 100 /* fastest */ /* Don't buffer the clock and reset lines */ set_dont_touch find (net, CLK) true set_dont_touch find (net, RESET_N) true /***********************************************/ current_design DECODER set_input_delay 10 -clock CLK all_inputs( ) >>/dev/null set_output_delay 10 -clock CLK all_outputs( ) >> /dev/null set_driving_cell -cell INV -library flex8000 all_inputs( ) >> /dev/null compile -map_effort low extract set_fsm_minimize true set_fsm_encoding_style one_hot set_fsm_minimize false compile -map_effort medium report_timing See State Machine Design on page 35 and State Machine Optimization on page 57. /***********************************************/ read -f vhdl./line_mon.vhd read -f vhdl./mailbox.vhd read -f vhdl./vm_caller.vhd /* top level */ create_clock CLK -period 100 /* fastest */ /* Don't buffer the clock and reset lines */ set_dont_touch find (net, CLK) true set_dont_touch find (net, RESET_N) true /* Setting Design Constraints*/ set_input_delay 14 -clock CLK all_inputs( ) >> /dev/null set_driving_cell -cell INV -library flex8000 all_inputs( ) >> /dev/null set_output_delay 24 -clock CLK all_outputs( ) >> /dev/null /* Setting Design Rule Constraints */ set_max_fanout 8 VM_CALLER check_design compile -map_effort medium -incremental_mapping /* save the database */ write -hierarchy -output "vm_caller.db" /* save, synopsys format */ /* writing edif */ write -format edif -hierarchy -output "vm_caller.edf" /* /* synopsys reports */ report_area report_cell report_clock report_constraint report_hierarchy report_timing See "Synopsys Optimization" on page 54. See Passing Data to MAX+PLUS II on page 58. See Synopsys Optimization on page Altera Corporation

21 Design Flow Figure 4. Synopsys dc_shell Script for the Voic Project (Part 2 of 2) /* include "syn2acf.cmd" command file to build a flat edif file, a constraint sdf file, and a timing sdf file. These will be used by the "syn2acf" constraint conversion program */ include /usr/maxplus2/synopsys/bin/syn2acf.cmd /* end of dc_shell script */ See Passing Data to MAX+PLUS II on page 58. After compilation, the Design Compiler reports the area shown in Figure 5 and timing shown Figure 6, which meet the original goal. Figure 5. Synopsys Area Report **************************************** Report : area Design : VM_CALLER Version: v3.2a Date : Sat Apr 29 17:34: **************************************** Library(s) Used: flex8000 (File: /usr/maxplus2/synopsys/library/alt_syn/flex8000/lib/flex8000.db) Number of ports: 71 Number of nets: 75 Number of cells: 3 Number of references: 3 Combinational area: Noncombinational area: Net Interconnect area: (No wire load specified) Total area: Altera Corporation 17

22 Design Flow Figure 6. Synopsys Timing Report (Part 1 of 2) **************************************** Report : timing -path full -delay max -max_paths 1 Design : VM_CALLER Version: v3.2a Date : Wed Jul 517:34: **************************************** Operating Conditions: Wire Loading Model Mode: top Startpoint: I1_DECODER/S23 (rising edge-triggered flip-flop clocked by CLK) Endpoint: I1_MAILBOX/ADDR_reg[1] (rising edge-triggered flip-flop clocked by CLK) Path Group: CLK Path Type: max Point Incr Path clock CLK (rise edge) clock network delay (ideal) I1_DECODER/S23/CLK (DFF) r I1_DECODER/S23/Q (DFF) f I1_DECODER/U175/A_OUT (TBL_1) r I1_DECODER/U152/A_OUT (TBL_5) r I1_DECODER/U200/A_OUT (TBL_4) r I1_DECODER/U202/A_OUT (TBL_5) r I1_DECODER/U203/A_OUT (TBL_1) f I1_DECODER/ACTION[1] (DECODER) f I1_MAILBOX/ACTION[1] (MAILBOX) f I1_MAILBOX/U575/A_OUT (TBL_1) r I1_MAILBOX/U565/A_OUT (TBL_4) r I1_MAILBOX/U482/A_OUT (TBL_1) f I1_MAILBOX/U571/A_OUT (TBL_2) f I1_MAILBOX/U617/A_OUT (TBL_1) r I1_MAILBOX/U597/A_OUT (TBL_3) r I1_MAILBOX/U762/A_OUT (TBL_2) r I1_MAILBOX/U599/A_OUT (TBL_1) f I1_MAILBOX/U566/A_OUT (TBL_7) f I1_MAILBOX/U672/A_OUT (TBL_1) r I1_MAILBOX/U480/A_OUT (TBL_1) f I1_MAILBOX/U692/A_OUT (TBL_9) f I1_MAILBOX/U693/A_OUT (TBL_6) f I1_MAILBOX/U694/A_OUT (TBL_9) f I1_MAILBOX/U695/A_OUT (TBL_1) r I1_MAILBOX/ADDR_reg[1]/D (DFF) r data arrival time Altera Corporation

23 Design Flow Figure 7. Synopsys Timing Report (Part 2 of 2) clock CLK (rise edge) clock network delay (ideal) I1_MAILBOX/ADDR_reg[1]/CLK (DFF) r library setup time data required time data required time data arrival time slack (MET) EDIF File Generation The dc_shell script for this project saves a hierarchical EDIF file using the EDIF generation parameters from the.synopsys_dc.setup file. This EDIF file is imported into MAX+PLUS II for compilation. MAX+PLUS II Compilation MAX+PLUS II automatically creates the file vmail.acf, which specifies all compilation settings. This file allows you to compile in batch mode in later runs, using the following command: maxplus2 -c vmail.edf 9 When this design example was first created, two modules did not achieve the timing goals. To correct this problem, you can use two design techniques: pipeline retiming and LCELL instantiation. These techniques are shown in VHDL Coding Techniques in this user guide. Using Peripheral Registers To minimize the Clock-to-output delays from the voic design, you can place output registers into the peripheral flipflops in the I/O elements (IOEs) on a FLEX 8000 device. To specify that output flipflops would be placed in an IOE register, a standard register that is directly connected to the top-level port is inferred. Altera Corporation 19

24 Design Flow Then, perform following steps in MAX+PLUS II: 1. Choose Global Project Logic Synthesis (Assign menu). 2. Turn on Automatic I/O Cell Registers. 3. Choose OK. 4. Compile the design. Forward Annotation To import detailed timing requirements from Synopsys to MAX+PLUS II, Altera provides the syn2acf utility. Figure 7 illustrates how to use the syn2acf utility. Figure 7. Using syn2acf # invoke the synopsys sdf to altera acf conversion utility # usage: syn2acf <design name>.edf /usr/maxplus2/synopsys/bin/syn2acf vm_caller.edf Post-Layout Simulation with Back-Annotated Timing Data After MAX+PLUS II synthesis and layout, you may wish to back-annotate the new functionality and timing information into Synopsys for a second synthesis optimization, using the timing information provided by MAX+PLUS II in the first compilation. In the future, Altera will offer the capability to generate timing information in a Standard Delay Format (.sdf) file during MAX+PLUS II. In addition, Altera will provide a library to translate the functionality back to Synopsys. VHDL Code for the Voic Project The full source code for the voic project is listed in Voic Sample File. 20 Altera Corporation

25 VHDL Coding Techniques July 1995 Summary Introduction This chapter presents a recommended VHDL coding style and shows how to use the DesignWare and instantiation capabilities of VHDL to craft optimal HDL designs for Altera HCPLDs. This information is intended to be used as a reference, where you can refer to a specific set of instructions on how to implement a specific function or take advantage of architectural features of the target device at the source-code level. The designer has maximum influence on the final performance and density of the target device in the original coding style of the hardware description language. Ideally, you should code your design as abstractly as possible to preserve technology independence. The design can become faster and smaller, however, as you design closer to Altera s architecture. The two ends of the spectrum are true technology independence and design for a specific architecture. Most designs will fall somewhere in the middle, balancing design portability and high performance. Technology-independent methods to code for efficient FLEX 8000 implementation are discussed in this chapter, and contrasted to technology-dependent methods. The effect of coding style on final circuit performance can be very dramatic. In some cases, circuit speed can be improved by a factor of three and utilization by a factor of two by making simple changes to source code. All examples in this guide are for FLEX 8000 devices. All VHDL code and code fragments use IEEE STD_LOGIC and STD_LOGIC_VECTOR types, which are contained in the std_logic_1164 package, unless otherwise noted. Generic Synthesis Strategies This section summarizes commonly accepted practices for effective synthesis with Synopsys. It is not a substitute for attending a full Synopsys synthesis training class. Novice users will benefit from reading High-Level Design Methodology Overview by Ken Nelson, located in the Synopsys on-line documentation; this document provides a good introduction to the synthesis design process. This overview and other information supplied by Synopsys is pertinent to users designing with Altera devices. Altera Corporation 21

26 VHDL Coding Techniques You should follow the synthesis guidelines listed below: Keep resources that might be shared between different functions or that might require a similar configuration (e.g., HDL constructs such as +) in the same block of the design hierarchy. Group similar designs into the same hierarchy, to allow Synopsys to share resources when practical. This process is known as resource sharing. Use the IEEE types contained in the std_logic_1164 package for your designs. Use of STD_LOGIC and STD_LOGIC_VECTOR types for Entity Declarations in your pre-synthesis register tranfer level (RTL) code is recommended. Although you can specify integer port types, a module will have STD_LOGIC port types when it is returned from the Design Compiler or MAX+PLUS II. You will be required to add conversion functions to integrate this with other not-yet-synthesized portions of your design. Pipeline high-speed sequential designs whenever possible. Keep related combinatorial logic together in a single block. This facilitates optimization of that block. Keep critical paths in a single block. Remove circuitry that is not speed critical from the critical path block. Register the outputs of lower-level files in the design hierarchy whenever possible. This process generates code that is easier to maintain and that can be more successfully synthesized. Registered outputs also make it easier to provide accurate timing constraints. Use a single Clock for each design block. Do not use deeply nested If Statements. Avoid using VHDL ports of mode BUFFER. In VHDL, when you need to make a reference to a port signal of mode OUT that is in a different architecture, you have three options: make the port of mode INOUT, make the port of mode BUFFER, or keep the port of mode OUT but create a dummy internal signal to drive it. Using a dummy signal is often the best method because it does not artificially create a bidirectional port. Use the INOUT port option only if you have a signal driver on the outside which you intend to feed back into the design. Avoid the use of BUFFER, because connected ports of any module higher up in the hierarchy must also be of mode BUFFER. Altera-Specific Synthesis Strategies With the MAX+PLUS II software, keep in mind that you will be resynthesizing the output of your final Synopsys-optimized design. This design flow has several side effects that should influence your design style. Grouping similar designs into the same hierarchy is good design practice and can be used to promote resource sharing in a hierarchical environment. MAX+PLUS II subsequently refines resource sharing decisions made by Synopsys Design Compiler. 22 Altera Corporation

27 VHDL Coding Techniques FLEX 8000 devices are register-rich; they provide a high ratio of flipflops to combinatorial logic. The architecture therefore makes pipelining and pipeline re-timing especially advantageous techniques for FLEX 8000 devices, since there is often little or no area penalty associated with using extra registers. This abundance of available registers also affects the design of finite state machines (FSMs). The more common binary or gray coding of FSMs is designed to minimize the usage of flipflops (minimal state vectors). However, one-hot encoding is typically the fastest state machine implementation available in the FLEX 8000 architecture. You can explicitly specify the encoding of state machines by mixing onehot and binary encoding schemes in the Synopsys FSM Compiler. This technique gives you a fine-grained control of the area/speed trade-off in state machine design. Instantiation vs. Inference In a given design, specific functionality can be implemented in two ways. You can infer the functionality from generic HDL code, or to have the most control, you can instantiate components or macrofunctions from the available libraries. Instantiation Explicitly select a technology-specific register element in the target library. For instance, you can partition the registers as separate components that you instantiate, and then connect to the synthesized portions of your design. Inference You direct the VHDL Compiler to infer latches or flipflops from your VHDL description with clearly defined methods that use If or Wait Statements. Table 1 shows the trade-offs of these two techniques. Table 1. Component Inference vs. Instantiation Method Advantages Disadvantages Inference Instantiation Easy to write. Leverages synthesis tools. You can specify exactly what you want. You can choose pre-defined, technology-specific blocks. Difficult or impossible to infer some components. Description is more difficult to generate. Design may become technology-specific. Altera Corporation 23

28 VHDL Coding Techniques The importance of technology-independence depends on your future plans for the design. Keeping the pre-synthesis source code technologyindependent allows you to re-target to other technologies at a later time, with a minimum of re-design effort. On the other hand, instantiation of Altera macrofunctions may be required to give the design added performance. These considerations are summarized in Table 2. Table 2. Technology-Independent vs. Technology-Dependent Design Design Style Advantages Disadvantages Technologyindependent Technologydependent Easily retargeted Promotes high-level design Uses design techniques optimized for speed or area Can re-use existing optimized modules May not achieve highest level of speed or minimal area May require detailed understanding of device architecture The following component specification techniques can be used when designing for FLEX 8000: Inference of HDL operators directly to FLEX 8000 gates Inference of supported HDL operators to Altera DesignWare implementation Instantiation of Altera DesignWare up/down counter Instantiation of Altera FLEX 8000 macrofunctions Instantiation of Altera primitives, such as LCELL, CARRY, and GLOBAL Basic Building Blocks Logic synthesis is still as much art form as it is a direct science. Designers new to synthesis often have an overly optimistic idea of what synthesis can do for them. More experienced users know that the tools must be guided toward an optimum solution, and there are many style, construct, constraint, and philosophical degrees of freedom to be explored. This section includes examples showing one or more methods to code common building blocks. It is not intended to be a complete list. From these descriptions, Synopsys infers logic for implementation in the Altera target architecture. All the sample files in this section are implemented using the types from the std_logic_1164 package. 24 Altera Corporation

29 VHDL Coding Techniques Level-Sensitive Latch A latch is inferred by any code requiring memory from one Clock cycle to the next. Because Synopsys reports when it is inferring components from your code, be sure to check these reports carefully. Unintended inferred latches are a common source of implementation errors for new users. In the FLEX 8000 architecture, Altera recommends using flipflops rather than latches because there is an abundance of flipflops: each logic element (LE) contains one flipflop. Latches are built by combining the combinatorial logic in the LE with feedback, and require more routing traffic and more area than flipflops. Altera encourages the Design Compiler to use registers over latches by employing an artificially high area penalty associated with LATCH in the flex8000.db library. Figure 8 shows a VHDL template for inferring a latch. 1 Altera recommends using latches for the MAX 5000 and MAX 7000 architectures. Figure 8. Simple Latch Inference PROCESS (datain, enable) IF enable = 1 THEN dataout <= datain; END IF; END PROCESS; Note that this style also implies an ELSE clause, as shown in Figure 9. Altera Corporation 25

30 VHDL Coding Techniques Figure 9. Implied ELSE Clause PROCESS (datain, enable) IF enable = 1 THEN dataout <= datain; ELSE dataout <= dataout; END IF; END PROCESS; In this example, the Design Compiler generates a latch to remember the value of dataout from one Clock to the next. Edge-Sensitive D Registers In contrast to latches, registers are inferred by the detection of the Clock edge, as shown below, using If Statements. (clk event AND clk = 1 ) Figure 10 through Figure 12 show HDL templates for creating registers with synchronous and asynchronous resets. The VHDL code shown in Figure 13 creates two synchronous 4-bit registers. Figure 10. DFF with Asynchronous Reset PROCESS(reset, clk) IF reset = 0 THEN dataout <= "0000"; ELSIF clk event AND clk = 1 THEN dataout <= datain; END IF; 26 Altera Corporation

31 VHDL Coding Techniques Figure 11. DFF with Synchronous Reset PROCESS(clk, reset) IF (clk event AND clk = 1 ) THEN IF reset = 0 THEN dataout <= 0 ; ELSE dataout <= datain; END IF; END IF; END PROCESS; Figure 12. Inferred, Synchronous Reset DFF Using WAIT PROCESS WAIT UNTIL clk event AND clk= 1 ; IF reset = 0 THEN dataout <= 0 ; ELSE dataout <= datain; END IF; END PROCESS; Figure 13. Inferred Registers with Asynchronous Reset PROCESS (clk, reset) IF reset = 1 THEN bus_b <= "0000"; bus_c <= "0000"; ELSIF (clk event and clk = 1 ) THEN bus_b <= bus_a; bus_c <= bus_b; END IF; END PROCESS; In general, the use of a Wait Statement also implies a register. The form required is very specific. WAIT UNTIL signame event AND signame = 1 ; -- rising edge Other forms of the Wait Statement (i.e., WAIT, WAIT ON, and WAIT FOR ) are not supported by the Synopsys Design Compiler. Altera Corporation 27

32 VHDL Coding Techniques Internal Tri-State Buffers Currently, Altera devices support tri-state buffers only at device I/O pins. A future version of MAX+PLUS II will support internal tri-state buses by converting them to multiplexers where appropriate. For HDL designs that already include internal tri-state buses, you can convert the internal buses to a multiplexer implementation within Design Compiler. Recompile after setting the following dc_shell switch: compile_assume_fully_decoded_tri_state_buses = true Compiling in Synopsys with this option turned on will convert tri-statable drivers on a bus to an n-bit-wide multiplexer driving the former bus signal. This coding change will make the design ready for implementation in Altera devices. Output Pad Tri-State Buffers Altera tri-state buffers are located at the device periphery, and can be used as follows: To drive an output port To drive internal logic connected to an INOUT port You infer this device simply by specifying a tri-state buffer driving a top level VHDL OUT or INOUT port. A tri-state buffer will be placed in a periphery location automatically. Figure 14 shows an example of inferring a tri-state buffer driving an output pad using VHDL. 28 Altera Corporation

33 VHDL Coding Techniques Figure 14. Tri-State Buffer Driving an INOUT Port ENTITY top IS port ( three_state : INOUT std_logic;... ); END TOP; ARCHITECTURE a OF top IS... SIGNAL two_state : std_logic;... PROCESS(enable, two_state) IF (enable) THEN three_state <= two_state; ELSE three_state <= z ; END IF; END PROCESS;... END a; 1 Note that the VHDL code in Figure 14 does not build a latch, because both the 1 and 0 conditions of the Enable pin are specified. I/O Pads No special action is required to specify that a port is a pad in VHDL. MAX+PLUS II interprets all ports at the top level of your design to be I/O pads. In the MAX+PLUS II Floorplan Editor, you can specify where the I/O pad is to be located on the device, or you can allow MAX+PLUS II to select the optimum location for timing and routing considerations. Unconnected I/O Pads Both Synopsys and MAX+PLUS II remove unconnected ports and logic. To reserve an unconnected pin in your device, place the desired port in the top-level entity in your HDL design, and then attach a DONT_TOUCH attribute on the port in the Design Compiler. To prevent MAX+PLUS II from removing this unconnected pin, assign the unconnected pin a location before compilation. Altera Corporation 29

34 VHDL Coding Techniques Flipflop in a Peripheral Location For input signals that require fast setup times, or output signals that require minimal Clock-to-output delay, you can use the registers available on the I/O pins in the FLEX 8000 devices. To specify that a flipflop will be placed in a peripheral location (inside an I/O element), infer a standard register that is directly connected to a top level port, as shown in Figure 15. Figure 15. Registering a Top-Level Output Port ENTITY top IS PORT (...; qout : OUT std_logic); END top; ARCHITECTURE a OF top is... PROCESS (clk, rst) IF rst = '0' THEN qout <= '0'; ELSIF clk'event AND clk = '1' THEN qout <= data; END IF; END PROCESS;... END a; Input pins can be handled similarly. Compile the EDIF file generated by the Synopsys tools with MAX+PLUS II. In MAX+PLUS II, you can either direct the Compiler to place all registers that are connected to pads in the periphery (global I/O registers), or you can specify each register individually. To specify that a register should be placed in the periphery, you must assign the I/O Cell Register logic option to the register before compilation. This procedure is detailed in Logic Synthesis Options. 30 Altera Corporation

35 VHDL Coding Techniques Counters Several good options are available for building counters in the FLEX 8000 architecture. Infer a simple counter. The Design Compiler will build it out of gates. Infer a DesignWare counter. Instantiate the DesignWare counter dw03_updn_ctr. Instantiate the Altera macrofunction a_8count. Design options for building an 8-bit counter with registered inputs and registered outputs are shown in Table 3. Table 3. Comparison of 8-Bit Counter Options Approach MAX+PLUS II Reported Area (LEs) Counter inference is shown in Figure 16. Registered Performance (MHz) Advantage Inference to gates Easy to infer dw03_updn_ctr Scalable a_8count Optimized Altera Corporation 31