Setup file.synopsys_dc.setup
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1 Setup file.synopsys_dc.setup The.synopsys_dc.setup file is the setup file for Synopsys' Design Compiler. Setup file is used for initializing design parameters and variables, declare design libraries, and so on. Shortly, the setup file defines the behavior of the tool and is required for setting the tool up correctly. The commands in this file are executed when Design Compiler is invoked. There are three different locations from where this file is searched for: The Synopsys root directory (<SYNOPSYS>/admin/setup/) for system-wide settings Your home directory ($HOME/) for user-defined settings The current working directory ($PWD/) for design-specific settings The files are read in the order shown above.
2 Setup file.synopsys_dc.setup Settings in user-specific setup file override the settings from system-wide setup file settings in design-specific setup file overrides settings from both system-wide and userspecific setup file You should have at least design-specific setup file for each of your projects.
3 Libraries target_library defines the technology library that Design Compiler uses to build the circuit. during technology mapping phase, Design Compiler selects components from the library specified with the target library variable to build the gate-level netlist. synthetic_library specifies the synthetic or Design Ware (DW) libraries technology-independent, microarchitecture-level design libraries providing implementations for various IP blocks adders, subtractors, comparators, building blocks for DSP, memories, advanced math functions, microcontrollers, etc
4 Directory Structure <PROJECT>/ -- project directory.synopsys_dc.setup -- Synopsys Design Compiler initialization file SRC/ -- HDL source files SYN/ -- synthesis subdirectory DB/ -- Database DDC/ -- Design Compiler database NETLIST/ -- mapped Verilog/VHDL netlists REPORTS/ -- reports SCR/ -- synthesis scripts WORK/ -- intermediate files from synthesis tool SIM/ -- simulation subdirectory (not needed in these examples) SCR/ -- simulation scripts WORK/ -- ModelSim work directory
5 mkdir lab2 cd lab2 mkdir src mkdir sym mkdir syn cd syn mkdir work mkdir db mkdir reports Example
6 Reading in the design consist of two tasks Analyzing (under File) Reads the HDL source files and checks them for syntactical errors Creates HDL library objects in an HDL-independent intermediate format and saves these intermediate files in a specified location Elaborating (top-module) (under File) Translates the design into a technology-independent design (GTECH) from the intermediate files produced during analysis Allows changing of parameter values (generics) defined in the source code Replaces the HDL arithmetic operators in the code with DesignWare components Automatically executes the link command, which resolves design references Check the elaboration reports to see the number and the type of memory elements Badly modelled hardware description may result as excessive or wrong type of memory elements inferred Uniquify top most level of design (under Hierarchy) makes unique the instances of the same reference design during synthesis Check design (under Design) If hierarchical design then use check_design -multiple_designs (command) Save design in ddc format Next time you can Read this ddc file
7 Optimizing the Design Design Compiler performs optimizations on three levels Architectural high-level optimizations which are performed on the HDL description level Logic-level performed on GTECH netlist and consists of two processes structuring flattening Gate-level works on the technology-independent netlist and maps it to the library cells to produce a technology-specific gate-level netlist
8 Architectural Optimizations Arithmetic Optimizations uses the rules of algebra to improve the implementation of the design. Design Compiler may rearrange the operations in arithmetic expressions according to the constraints to minimize the area or timing Resource Sharing tries to reduce the amount of hardware by sharing hardware resources with multiple operators in your HDL description Without resource sharing each operator in your code will result as a separate HW component in the final circuitry. Selecting DesignWare Implementations the implementation selection of a particular resource is left to the Design Compiler. For example, the Basic IP Library contains two implementations (ripple and carry-lookahead) for the +-operator (the DesignWare Foundation Library provides more implementations for the '+' and other operators). When selecting DesignWare implementation, Design Compiler considers all available implementations and makes it selection according to your constraints. At this point, the design is represented by GTECH library parts (i.e. generic, technology-independent netlist).
9 Logic-level Optimizations Structuring evaluates the design equations represented by the GTECH netlist and tries by using Boolean algebra to factor out common subexpressions in these equations. The subexpressions that have been identified and factored out can then be shared between the equations. For example, Before Structuring P = ax + ay + c Q = x + y + z After Structuring P = ai + c Q = I + z I = x + y Structuring is usually recommended for designs with regular structured logic CLA, multiplies, Flattening (sometimes makes design big) converts logic into two-level, Sum-of-Products representation Flattening produces fast logic (by minimizing the levels of logic between the inputs and outputs) at the expense of the area increase Flattening is recommended for designs containing unstructured or random logic
10 Gate-level Optimizations Mapping maps the cells from technology-independent netlist (GTECH) to the cells in library specified by the target_library variable. Delay Optimization fixes the timing violations introduced by mapping phase. Design Rule Fixing fixes the design rule violations in the design. Design Compiler inserts buffers or resizes existing cells design rule fixing phase is allowed to break timing constraints. Area Optimization the last step that Design Compiler performs on the design. During this phase, only those optimizations that don't break design rules or timing constraints are allowed.
11 Specifying Clocks and Clock Networks two clock types in SYNOPSYS real clocks Real clocks have sources ideal» no delay through the clock network. Propagated» opposite of ideal clock virtual clocks has no sources
12 I/O delays set_input_delay How long after clock rising edge, input is available. This 'input_delay' will assume that your design is driven by a DFF This external delay is subtracted from the clock period and the margin specifies how much time is left for the internal logic. set_output_delay How long before clock rising edge, output must be available your design is driving a DFF This external delay is subtracted from the clock period and the margin specifies how much time is left for the internal logic Default = 0
13 Some constraints set_dont_touch rst_n set_ideal_network rst_n
14 Continue with Synthesis Compile design (under Design) Start with medium effort See new Schematic (under Schematic) See Critical Path (under Select) Paths From/Through/to (with delay type: max) See reports if your constraints have been met Checking the Timing (under Timing) Report Timing Path Checking the Area (under Design) Report Area Checking the Power (under Design) Report Power Save design in ddc format with different name
15 Optimizations Design flaws from the synthesis point of view Too many levels of hierarchy Hierarchical cells are too small Design Compiler operates only within a single block at a time If design has very small modules, Design Compiler cannot perform optimizations on design manipulate hierarchy described in VHDL code
16 Optimizations Remove old designs (under File) Read the last ddc file Compile (under Design) With Medium effort Ungroup, Autoungroup and Incremental checked
17 Optimizations Read the last ddc file Ungroup modules you want and Compile with High effort (under Design) Or Compile with High effort (under Design) while Ungroup, Autoungroup and/or Incremental are checked Or Compile Ultra (under Design) Save the design
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