Glossary. AHDL A Hardware Description Language, such as Verilog-A, SpectreHDL, or VHDL-A, used to describe analog designs.

Transcription

1 Glossary ADC, A/D Analog-to-Digital Converter. AHDL A Hardware Description Language, such as Verilog-A, SpectreHDL, or VHDL-A, used to describe analog designs. AMBA Advanced Microcontroller Bus Architecture. An on-chip bus released by advanced rise machines (ARM). AMS Analog/Mixed Signal. The combination of analog and digital technology on the same integrated circuit (1C). APB Advanced Peripheral Bus. An on-chip bus released by advanced rise machines (ARM). ARM7TDMI A family of RISC processors from Advanced Rise Machines (ARM). Refer to for more details. ASB Advanced System Bus. An on-chip bus released by advanced rise machines (ARM). ASIC Application Specific Integrated Circuit. ATE Automatic Test Equipment.

2 362 SOC Verification ATM Automatic Transfer Mode. ATPG Automatic Test Pattern Generator. RDM Background Debug Mode. An on-chip debug mode available in Motorola microcontrollers. BFM Bus Function Model. BIC Bus Interconnection Device. BLC Bluetooth Link Controller. Bluetooth An open protocol standard specification for short-range wireless connectivity. Refer to for more details. BSP Board Support Package. C, C++ Programming languages used for software development. CAD Computer Aided Design. CAS Cycle Accurate Simulator. CBS Cycle-Based Simulation. Certify An FPGA synthesis, partitioning, and configuration tool available from Synplicity. Chip A single piece of silicon on which a specific semiconductor circuit has been fabricated. ConCentric A system-design tool available from Synopsys. Core A complex, pre-designed function to be integrated onto a larger chip, such as PCI, MPEG and DSP functions, microprocessors, microcontrollers, and so on. The core is also called a macro, block, module, or virtual component. COSSAP A system-design tool available from Synopsys. Coverscan A code coverage tool available from Cadence.

3 Glosssary 363 DAC, D/A Digital-to-Analog Converter. DEF Design Exchange Format. A Cadence format used to describe physical design information. Includes the netlist and circuit layout. Design flow The process of a chip design from concept to production. Design house A company specializing in designing ICs, but has no in-house manufacturing and does not sell its designs on the open market. Design reuse The ability to reuse previously designed building blocks or cores on a chip for a new design as a means of meeting time-to-market goals. Design rules Rules constraining IC topology to assure fabrication process compatibility. DFT Design For Test. Refers to specific activities in the chip design process that provide controllability and observability to determine the quality of the product. DMA Direct Memory Access. DRAM Dynamic Random Access Memory. DRC Design Rules Check DSM Deep Sub-Micron. DSP Digital Signal Processor. A high-speed, general-purpose arithmetic unit used for performing complex mathematical operations. DUT/DUV Design Under Test/Design Under Verification. EBS Event-Based Simulation. EC Formal Equivalence Checking. ECO Engineering Change Order. EDA Electronic Design Automation. Describes a group of CAD tools used in the design and simulation of electronic circuits. EDA tools allow designers to describe and test the performance of circuits before they are implemented in silicon. The

4 364 SOC Verification EDA suppliers include Cadence, Synopsys, Mentor, and a host of smaller vendors. Refer to for more details on EDA companies and the products they offer. EDIF Electronic Design Interchange Format. EPROM Erasable-Programmable Read-Only Memory. ERC Electrical Rules Check. Equivalence Checker A formal equivalence checking tool available from Cadence. ESW Embedded Software. Fault Coverage A measure that defines the percentage of success a test set has in finding simulated stuck-at-0 or stuck-at-1 faults for a list of nodes in a given design. FFT Fast Fourier Transform. FIFO First In First Out. Firm Core IP building block that lies between hard and soft IP. Usually these are soft cores that have been implemented to fully placed netlists. FormalCheck Model checking tool available from Cadence. FPGA Field Programmable Gate Array. An IC incorporated with an array of programmable logic gates that are not pre-connected, and the connections are programmed by the user. Foundry Semiconductor company that fabricates silicon chips. FSM Finite State Machine. Gate Basic circuit that produces an output when certain input conditions are satisfied. A single chip consists of millions of gates. GDSH Graphical Design System II. An industry standard format for exchanging final IC physical design data between EDA systems and foundries or mask makers. GDSII is a Cadence standard.

5 Glosssary 365 GSM Global System for Mobile communications. World s first standard for mobile communications. GUI Graphical User Interface. Hard IP Complete description of the circuit at physical level. Hard IP is routed, verified, and optimized to work within specific design flows. HDL Hardware Description Language. A high-level design language in which the functional behavior of a circuit can be described. VHDL and Verilog are HDLs that are widely used. HDL-A Hardware description language for describing analog designs. HW/SW Hardware/Software. HW/SW co-design Design methodology that supports concurrent development of hardware and software to achieve system functionality and performance goals. HW/SW co-simulation Process by which the software is verified against a simulated representation of the hardware prior to system integration. HW/SW co-verification Verification activities for mixed hardware/software systems that occur after partitioning the design into hardware and software components. It involves an explicit representation of both hardware and software components. IACK Interrupt Acknowledge. IC Integrated Circuit. ICE In-Circuit Emulator. IEEE Institute of Electrical And Electronic Engineers. IEEE-1284 Standard for personal computer parallel ports. IEEE-1394 High-speed serial bus. Also called a firewire. I/O Input/Output.

6 366 SOC Verification IP Intellectual Property. IP is the rights in ideas that allow the owner of those rights to control the exploitation of those ideas and the expressions of the ideas by others. IP includes products, technology, software, and so on. IR Drop Current-resistance drop. IRQ Interrupt Request. ISR Interrupt Service Routine. ISS Instruction Set Simulator. JPEG Joint Photographic Experts Group. Industry standard for the digital compression and decompression of still images for use in computer systems. JTAG Joint Test Access Group. IEEE standard for device scan. LA Logic Analyzer. Layout The process of planning and implementing the location of IC devices within a chip design. LEF Library exchange format Logic BIST Logic Built-In-Self-Test. LVS Layout Versus Schematic. Manufacturing test Physical process of validating and debugging the performance and functional operation of semiconductor chips/products. Micron One-millionth of a meter, or about forty-millionths of an inch ( inches) MPEG Moving Picture Experts Group. Industry standard for the digital compression and decompression of motion video/audio for use in computer systems. MUX Multiplexor. NC-Verilog Simulation tool available from Cadence.

7 Glosssary 367 Netlist Complete list of all logical elements in an IC design, together with their interconnections. N2C System design solution available from CoWare. OPC Optical Proximity Correction. OVI Open Verilog International, a Verilog HDL standard body. PCB Printed Circuit Board. PCI Peripheral Component Interconnect bus. PE Parasitic Extraction. PLD Programmable Logic Device. PLI Programmable Language Interface. PLL Phased Locked Loop. Process Steps by which the ICs are constructed for a given technology. PROM Programmable ROM. ROM that can be programmable by the user. PRPG Pseudo-Random Pattern Generation. Protocol Formal definition of the I/O conventions for communications between computer systems and peripherals. Prototype Preliminary working example or model of a component or system. It is often abstract or lacking in some details from the final version. PSM Phase Shift Mask. RAM Random Access Memory. RE ROM Emulator. RF Radio Frequency.

8 368 SOC Verification RISC Reduced Instruction Set Computer. ROM Read Only Memory. RPS Rapid Prototyping System. RTL Register-Transfer Level. RTOS Real Time Operating System, such as VxWorks, psos, or Windows CE. SDF Standard Delay Format. Semiconductor manufacturer A firm that is active in the business of designing and producing semiconductor devices. SI Signal Integrity. Simulation Simulating a chip design through software programs that use models to replicate how a device will perform in terms of timing and results. SOC System-On-a-Chip. An IC that contains the functional elements of an entire electronic system, such as a computer, PDA, or cell phone. SOC designs involve integrating CPU, memory, I/O, DSP, graphics accelerators, and other components on a single chip. Soft core Soft core is delivered in the form of synthesizable HDL code. Specman Elite A testbench-generation tool available from Verisity. SpectreHDL Cadence designs. hardware description language that describes analog SPF Standard Parasitic Format. SPICE Simulation Program With Integrated Circuit Emphasis. SPW Signal Processing Worksystem. Signal processing system design tool available from Cadence. SRAM Static Random Access Memory.

9 Glosssary 369 STV Static Timing Verification. TBV Transaction-Based Verification. TCL Tool Command Language. TestBuilder Testbench authoring tool available from Cadence. TRST Transaction Recording System Task calls. TTM Time to Market. TVM Transaction Verification Model. UART Universal Synchronous Receiver Transmitter. USB Universal Serial Bus. VCC Virtual Component Co-design. System design tool available from Cadence. Vera Testbench generation tool available from Synopsys. Verification Pre-silicon process that is used during the design phase for gaining confidence that the design will produce the expected results. Verilog Industry-accepted standard HDL used by electronic designers to describe and design chips and systems prior to fabrication. Verilog-A/MS HDL for describing analog/mixed signal designs. Verilog LRM Verilog Language Reference Manual. Verilog-XL Verilog simulator available from Cadence. VHDL VHSIC Hardware Description Language. VHDL-AMS Hardware description language for describing analog/mixed signal designs. VHSIC Very High Speed Integrated Circuit.

10 370 SOC Verification VC Virtual Component. A design block that meets the VSI Specification and is used as a component in the virtual socket design environment. Virtual components can be available in three forms: soft, firm, or hard. VCS simulator A simulation tool available from Synopsys. Virtual Prototype Computer simulation model of a final product, component, or system. VSI Virtual Socket Interface. Set of standards to enable the exchange of IP building blocks. VSI is supported by the VSI Alliance, a 148-member group that was formed to address the complex problem of establishing comprehensive standards for the exchange of IP components between semiconductor companies.

11 Index 371 Index A APB bridge verifying with FormalCheck 99 ASB bus protocol checker 169 ASB arbiter verifying with FormalCheck 97 ASB decoder verifying with FormalCheck 102 ASB interface 40 ASB master protocol checking code 115 ASB slave model 167 B Black box feature 328 C check_data task 112 Clock-tree synthesis 329 Code coverage analysis types of 9 Code coverage, HDL level 52 Computation tree logic (CTL) 92 Conditions, success and failure 50 Constraints for formal verification 96 model checking 93, 94 Counterexamples equivalence checking 329 model checking 95 Coverscan Analyze 122 Coverscan Recorder 122 D Debugging model checking failures 95 Design partitioning 26,56,231 E Emulation configurable logic 53 systems 10 Equivalence checking black box feature 328 clock-tree synthesis 329 constant propagation 327 design exclusion 327 directives 326 issues 326, 328 logic timing across latch boundaries 327 pragmas 326 scan insertion 328 state encoding 327 types of gate-to-gate 328 F Finite state machines equivalence checking 327 FormalCheck constraints 96 Functional coverage 206 H Hard prototype ASB interface 40 Hardware acceleration 11, 54 Hardware modeler 54 L Latches 327 M Metrics, verification 35 Migrating test suites 57 Migration RTL-to-netlist 22 Mixed-level simulation 55 Model checking capacity 90 constraints, types of fairness 94 safety 94 counterexamples 95 debugging 95 design partitioning 95 environment modeling 95 methodology flow 90 properties 91 extracting 94 failures 95 Models behavioral 33 functional 33

12 372 SOC Verification gate-level 133 creating 50 pin accurate 25 metrics 51 protocol-based communication 25 migration 56 sources 33 token-based 25 T token-passing 25 TBV 9 Temporal modalities 92 N Temporal operator Netlist verification path quantifier 92 netlist views 331 temporal modalities 92 Testbench migration 57 O Testbenches Over-constrained 93 bit-true representations 21 fixed-point representations 22 P system-level53 Path quantifier 92 Test suite 50 Precoverscan 122 Test suite coverage, metrics 52 Properties Transaction migration liveness 92 functional-to-rtl 22 safety 91 RTL-to-netlist 22 specification language 92 Transaction verification module strong liveness 92 test program example 202 Protocol-checking testbench Transaction verification module (TVM) 34 creating 109 Transaction wrappers 156 Transaction-based verification 9 R TVM 9 Rapid prototype 10, 231, 238, 286 Types, metrics 52 Regression testing 35 V S Verification Scan insertion 328 flow 16, 26 Slave watcher metrics 34 example 170 plan 31 Slave watcher conditions tools 32 example 175 Slave wrapper example 168 State variables in formal verification FormalCheck state variables 97 Stimulus 34 Success and failure conditions 50 Synthesis clock-tree 329 state encoding 327 System-level test suite 50 application 52