The Application of SystemC to the Design and Implementation of a High Data Rate Satellite Transceiver
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1 The Application of SystemC to the Design and Implementation of a High Data Rate Satellite Transceiver The MITRE Corporation Approved for public release. Distribution unlimited. Case # Contract No. FA C-0001, and is subject to the Rights in Technical Data The MITRE Corporation. All Rights Reserved
2 Introduction Application is next gen. high data rate military satcom modem Multi-FPGA design, > 100M eq. ASIC gates Must be ported across various HW platforms Platform 1 Platform 2 Platform 3 Platform 4 2
3 Motivation for a System Level Language, Flow Highly complex datapath system RTL simulations become slower Debugging RTL on platform becomes impractical Simulink models become too abstract Not efficient tool for modeling platform specifics Platforms have varying resources FPGAs, transport, GPPs, DSPs all differ Software porting may be considered 3
4 Proposed Language: SystemC Suited for highly abstract modeling Enables quick development of platform models Excellent for HW/SW co-simulation Easy to model heterogeneous platforms Open source reference simulator Can run simulations without commercial licenses Based on C++ Can leverage extensive libraries Can be modified to run on a GPP, DSP Everybody knows C 4
5 Flow Overview: Algorithm model Architecture GUI Automated XML generated SystemC/RTL generated C++ models RTL models Simulation Deployment Flow was designed to shorten schedule by automatically generating all SystemC infrastructure, vastly reducing efforts of the end user 5
6 Flow Detail: Algorithm Model Fixed-point Simulink models designed for each parallelization level Data generators and checkers developed Test vectors generated at block boundaries Algorithm model Architecture GUI XML generated SystemC/RTL generated Simulation C++ models RTL models Deployment F(x) G(x) H(x) Legend Infrastructure Data Generator Performance Checker Performance Checker Performance Checker Inifinite precision worker F(x) G(x) H(x) Limited precision worker 6
7 Flow Detail: System Architecture GUI GUI used to lay out system architecture Users enter blocks, ports, properties Connect to channels Draw FPGA boundaries GUI generates XML with push of a button Algorithm model Architecture GUI XML generated SystemC/RTL generated Simulation C++ models RTL models XML contains descriptions of: Modules/instances Connectivity Parameters Verification test points Deployment 7
8 Flow Detail: System Architecture GUI Channel SystemC Component RTL Component 8
9 Flow Detail: SystemC Code Generation XML fed to code generation scripts Generates wrappers, top level Wrappers translate between SystemC and worker interfaces Top level instantiates, binds system Workers verified using data from Simulink models Algorithm model Architecture GUI XML generated SystemC/RTL generated Simulation Deployment C++ models RTL models Timing can be inserted for approximate platform modeling Following infrastructure used for verification: Data generators, checkers Diagnostic channels Logging facilities 9
10 Flow Detail: SystemC Code Generation 1. Write or reuse an existing C++ model Automated 2. Put a simple SystemC wrapper around C++ model 3. Insert wrapped model into environment SystemC Top Level SystemC Wrapper SystemC Wrapper SystemC Wrapper C++ h(x) C++ g(x) C++ f(x) 10
11 Flow Detail: RTL verification User writes wrapper with flow control signals OCP wrapper generated around user wrapper SystemC top-level file generated Instantiates and binds all modules Adapters translate from SystemC interfaces to OCP Algorithm model Architecture GUI XML generated SystemC/RTL generated Simulation Deployment C++ models RTL models SystemC, RTL co-simulated with commercial simulator Verification is directed and random Simulink test vectors used for directed Linear feedback shift registers used for random Probes inside channels capture, verify data 11
12 Flow Detail: RTL code generation 1. Write or reuse an existing RTL model Automated 2. Put an OCP interface wrapper around RTL model SystemC Wrapper 3. Instantiate OCP wrapper from a SystemC wrapper 4. Insert fully wrapped model into environment OCP Wrapper SystemC Top Level SystemC Wrapper C++ h(x) SystemC Wrapper OCP Wrapper RTL f(x) RTL f(x) SystemC Wrapper C++ g(x) 12
13 Results Subset of modem ported to second platform in ~2 staff weeks > source lines of code > SLICEs Automation allows more effort towards verifying functional blocks SystemC simulation performance: Simulation Data Rates SystemC 8298 RTL Data Rate (samples/s) 13
14 Summary Flow has several benefits and limitations: Benefits Facilitates more thorough verification through co-simulation Reduces time to repartition, redeploy through automation Enables application to be developed independent of target hardware Isolates designers from SystemC details while still leveraging advantages Fosters reuse through standard interfaces LImitations Increased simulation time Offset by reduced development time 14
15 Future Work Integrate behavioral synthesis Better support for performance modeling Better support for HW/SW co-simulation Adopt SystemC TLM Standard Adopt SCV 15
16 Q&A 16
17 Extra Slides 17
18 Flow Detail: Zeligsoft GUI 18
19 Why SystemC? SystemC and SystemVerilog were considered SystemVerilog Very easy to integrate with HDLs Built in feature-rich verification facilities Good for quickly producing testbenches Moving towards higher levels of abstraction Vendor implementations differ, but are converging SystemC Better suited for highly abstract modeling Excellent for HW/SW co-verification Open source reference simulator vendor neutral Based on C++ _Can leverage extensive libraries _Can be modified to run on a GPP, DSP _ Everybody knows C SystemC seemed a better match for our needs 19
20 Detailed Requirements Greater than 100 Mbps; Greater than 100MHz BW High levels of parallelization Multi-FPGA implementation High performance FEC used to achieve ultra-low Bit Error Rates (BER) Less than 10e-7 BER at SNR < 5dB Drives FPGA resource requirements Multi-mode operation 2 modulation schemes Multiple data rates Portability Needs to be highly portable 20
21 Flow Detail: RTL code generation User may need to write wrapper with flow control signals OCP wrapper generated around user wrapper Defines ports, contains logic for three OCP profiles: Unidirectional streaming data Bidirectional addressed data System control signals (interrupts, state information) Instantiates worker entity Automatically maps data into records User wires worker ports to data and control signals 21
22 Flow Detail: RTL co-simulation SystemC Wrapper Data Source C++ f(x) Data Sink SystemC Wrapper OCP Adapter OCP Wrapper RTL f(x) OCP Adapter 22
23 Flow Detail: RTL Deployment Gaskets are developed for the host platform Instantiated on the boundaries of each FPGA Translate from OCP to platform-specific interfaces Design top levels generated for each FPGA Instantiate and bind all OCP-wrapped workers Connects workers with OCP channels Debug visibility controlled with a generic FPGA top levels are hand-written Instantiate and bind design top level VHDL file and gaskets 23
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