In-Circuit Functional Test ATE Tools

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1 In-Circuit Functional Test ATE Tools Today many tools are available to test a PCB either in the production line and for repair purposes. In this article we ll try to highlight the basic principles behind the ATE and how a company could benefit of it with a look at the market. First of all we should notice that an ICT is nothing but an ATE but the ATE may NOT be an ICT. For example the optical inspection of a PCB on the production line is a specific ATE often named AOI system. In this case there is no electrical contact with the UUT so the AOI is a specific ATE but not an ICT. In the market are also available low-cost ATE named Defect Analyser. These ATE perform standard tests on a limited number of devices and are usually not fully programmable. ICT Basic Principles The working concept is the same both for an ASIC s ATE or an ICT. The system basically generate a pattern or a sequence of test vectors and measure the response from the UUT. This response is compared with a test program that is stored on the Hard Disk. If the response match the test program then the test Pass otherwise it Fail. Test vectors can be digital or mixed, depending on the device or UUT. For example suppose we want to test a NOT_Gate. Then the test vector could be 1001 meaning that the ICT will Drive one at the input, then Sense zero at the output (the first two bit ). The same is done for the last two bit 01. This way the functionality of the device is fully tested. In this example we need an ICT that should be able to Drive and sense a total of 4pins (1001), named PinDrivers. Today s ICT are available from 48 upto more than thousands PinDrivers. Sometimes, however, may happen that a UUT pass the test but do not work on the field, why? To understand this we ve to consider the difference between a Functional test and a RealTime test. RealTime Test In the previous example we ve tested a NOT_Gate using the ICT so we ve done a functional test. However when the UUT is working on the field the timing of the signals are given by the clock that is present on board rather than controlled by the ICT. In this case the NOT_Gate may work properly when stimulated with the relatively low frequencies from the ICT but may fail when stimulated with the higher frequencies coming from the UUT s oscillator. The frequency of the test vectors, more properly named thetestrate, can vary from different makers and it s an important parameter of the ICT. The TestRate is usually given in us (microseconds) and the smaller the faster is the test speed. However it s important to understand that increasing the TestRate do not transform the functional test into a RealTime test. All the 1

2 ICTs in fact are designed to measure an electrical value not a time value. All the ICTs are basically Functional testers. For example suppose we have a DAQ which will read data from memory every 120ns. Consider a commercial SRAM with the timings given below : Here the Read Cycle time is exactly 120ns, however if for some reason we try to read a little bit faster, then the SRAM will not be able to come out with data in time. In this case our UUT may have some intermittent problems often tough to debug. We can notice that when we test the SRAM with the ICT this device will Pass but when we plug the PCB on the field then it will probably fail. Position of the ICT In the previous example we ve seen that a RealTime problem cannot be detected by an ICT. For this type of problems the use of LSA, DSO or ICE is recommended and it s a normal practice in the lab. After the prototype has been debugged then we can go for production. In the production line we expect only functional faults ; typically open and shorts or even faulty devices. It s interesting to notice that the test programs used in production can also be used to repair the UUT. The ICT can be used mainly in three areas: Production Line Repair Device screening 2

3 We can summarize the production cycle as in the figure below: Types of Tests A good ICT can be programmed to perform typically three types of tests, all mixed signals : DeviceTest EdgeCard Test Bed of Nail Test SystemTest The DeviceTest is done usually with test-clips placed over the device. This ensure good contacts between the UUT and the ICT. This test can be done InCircuit or out-circuit in case of device screening. The EdgeCard Test is done connecting the edge-card-connector, when available, to the ICT. This way the entire PCB can be tested. In this case the Test Engineer will provide a TI and the Test Program after having evaluated the schematics that are required for this type of test. A good value for the TI could in the range of 70% 90%. This test is feasible in production and is cost effective compared with the Bed of Nail Test. The Bed of Nail Test is done placing the PCB over a test fixture that have a collection of nails exactly placed so that the corresponding pads existing on the PCB get contacted with the nails. This is the typical test done in production where the TI can be 100%. The SystemTest typically is performed on the whole system thru a connector. The system can be a chassis with many boards inside or even a single PCB. This type of test can identify the faulty board in the system as well as the faulty device on it. Writing the test program for this type of test may require a long time using the traditional approach of coding the instructions in a Test-Language. This depend on the complexity of the system and on the types of tests to be performed. 3

4 An alternative is offered by the latest generation of ICTs. For example the most advanced ICT have the option to incorporate multiple SwithMatrix and a GUI of the type Drag and Drop. This way a system test or even an EdgeCard Test can be performed without writing a single line of code. Built-In instruments Many ICT have internal instruments incorporate in the system. These can be used to stimulate the UUT and to acquire the outputs. Then many analysis could be done on the signals especially if the ICT can inject analog signals other than digital only. For example we could measure the return Loss from a PCB injecting a sinewave at, let say 2Mhz then calculating the power spectrum for the reflected signal in Db centred at that frequency. The most advanced ICT incorporate arbitrary signal generators, DMM, FCT and DSO all of them controlled by the GUI. Here we should recognize that the internal instruments should be fully controlled by the ICT both thru a coded-program or a graphical-program otherwise the ATE become a manual Test-Equipment. Backdriving Many more things have to be taken in account while testing a device and in particular when the test is done InCircuit. In this case the Backdriving principles should be clearly understood since it play a key role in every ICT. In order to test a device or component in a powered up circuit, it is necessary to force the input conditions to both a logic 1 and 0 while testing. This input may be connected to a device output in an active condition and the force applied to the device output can stress it beyond its design limits, thus causing the device to fail obviously this is unacceptable, and the procedure, known as Back Driving must be operated in such a way that the forcing effect on the output stage does not cause a failure od the device. The principle of Back Driving can be seen below. Under normal drive conditions the output transistor Q1 would be required to sink 16mA x 0.4 Volts 4

5 However durlng the test cycle of the NAND the collector/emitter junction provides the Back Drive leakage path and would be required to dissipate a current of say 150mA at 3.5V (525mW) Therefore to protect the junction, the time held in Back Drive is limited to a maximum of 25mS, with an ON to OFF ratio of 1 to 20 this means that for every Back Drive operation the junction is allowed to relax for 0.5 seconds, thus ensuring that no damage is done to the device. This principle comes from a long term study named INT-DEF-STD-0053 which ensure that no damage will occur on the devices present on the PCB when the max. duration of the test is within 25ms. The TestRate, the Current Sink/Source and the RAM behind each pin are all features related each others and with the Backdriving principle. Test Rate We can define the TestRate as the interval of time between one test vector and the next and is normally given in useconds. The TestRate is related with the Backdriving principle we ve seen before. For example consider to test the commercial FIFO 7205 that is organized as 8Kx9. This is a special register where the first data stored comes out first. For this simple test, just an example, we ll Write the same data in every register then check if we Read the same back. The signals of interest are : R = pin for Read W = pin for Write Data = Data bus A typical test to Write the FIFO could be implemented like this: K = 0; While (K <= 8190); { Store Data; Clock W; K++; } // Data is placed on the Data-BUS // One clock pulse on W, Data is stored inside the FIFO // increment K Here we ve three instructions for every loop, this will translate in three test vectors for every loop in order to Write the FIFO with the value contained in the variable Data. Because the FIFO is 8K deep then we have 8,190x3 test vectors to Write and the same to Read the FIFO. In order to test the FIFO we ll need at least 49,140 test vectors to be generated in max 25ms. It s clear that if our FIFO is, for example 32K deep then to test it, we need about 32kx3 + 32kx3 that is more than 192,000 test vectors in 25ms. How much should be the min. TestRate in order to test this device? It should be 25ms divided by 192 that is 0.13uS or 7.68Mhz. A good ICT today can reach TestRate in the order of 25Mhz while testing a PCB with a Bed of Nail fixture. The test of the FIFO is just an example, other devices need an adeguate TestRate to be fully tested. For example suppose we need to test a commercial 1Mx16 DRAM. If we proceed with a code-program like 5

6 for the FIFO then we may need at least 1million test vectors to Write and the same to Read. In 25ms this translate in a TestRate of about 25/2000 that is or 80Mhz. In this case the advanced ICT provide an alternative using an internal Macro function that is faster than the coded-program and can be setup to test only some predefined cells of the memory so that this type of DRAM can be tested with just 4Mhz. An other example is when we need to test complex ASICs where the number of test vectors can easily come to 250,000 or more. In this case 25/250 = 0.1uS that is 10Mhz. Sink/Source Current The ICT must be capable to source enough current to the UUT and to Sink or absorb an equal amount of current. The source / sink capability of the ICT can best be explained by using diagrams. When a pin of a Device goes faulty there are 2 extremes of condition: Open Circuit: The Nodal Impedance that the test system experiences is no worse than when Back-Driving into a good component and therefore presents no problem to the system Short Circuit: Due to the manufacturing structure an Integrated Circuits, whereby I / O transistor stages of a device are embedded within a substrate layer, it is unusual for a Short Circuit pin on a Device to exhibit a dynamic impedance of less than 4 Ohms. If the ICT can Drive into a 4 ohm Ioad and still generate a valid logic 1 then other devices on the node can be tested successfully. See figure below. The voltage Vout = Vin*RL/ (RL+RS), this means about 2.4V when about 600mA are supplied by the ICT. However this current is approximate and in practical it s found that the supplied current should more than 600mA on all channels to drive properly the UUT for InCircuit test. 6

7 RAM behind each pin The RAM behind each pin is again related with the TestRate of the ICT and the Backdriving principle. In the example of the FIFO we have used about 192,000 test vectors to test it. We know that these test vectors have to be generated in max. 25ms and this means that we should arrange some space to keep them ready before the test start. This space is the RAM behind each pin. Now the question is how much RAM we need to store these 192,000 test vectors? Of course 192K RAM behind each pin can do the job but, this way the ICT may become even more expensive and, moreover, it s not required. In fact a good ICT include an optimization algorithm that strictly uses the required amount of memory depending on the test program. For example if our FIFO is filled with the same Data in every location than, to simplify, we need just one byte behind each pin to Write and one byte to store what is Read from it. Of course this is a simple example, consider a 32Kx8 SRAM where we ve to generate 32K addresses. In this case again the ICT have an optimization program which know that while we re testing,let say the LSB, the MSB do not change so it can optimize on the memory usage for that pin driver. Because the devices are more and more complex, the general rule is Bigger, Better. Guarding Guarding is required primarily when the outputs of the Device under Test are connected to the outputs of other devices in a "wired-or" or "tri-state" configuration. There are two types of Guard, each of which can be either a Standard Driver / Sensor channel, or an Auxiliary Driver / Sensor channel. STATIC GUARD Static Guards are active drive signals applied to a device for the entire duration of the FUNCTIONAL Test of the device in which the Guards have been programmed. Examples of the use of Static Guards are explained in the above circuit diagrams. DYNAMIC GUARD Dynamic Guards can be programmed to be either Drive or Sense, and the state of the Dynamic Guard can be changed during the Functional Program i.e. they can be used in exactly the same way as the standard Driver / Sensor channels. 7

8 Examples of this are shown in the following figures: 8

9 In the above circuit devices U8 and U9 are connected together onto a Data Bus. Whilst testing (or programming) U8, it is necessary to "isolate" (Tri-State) U9 from the Data Bus otherwise erroneous results will occur. To achieve this "isolation" U9 is "GUARDED" from U8 by connecting a logic I to pin 19. Conversely when testing U9, U8 is "Guarded" by attaching a Guard point (programmed to a logic 1). A "wired-or" is very similar to the above example, except the outputs of the "Guarded" Devices are required to be programmed to a logic I level by the implementation of the Guards. A further example of the use of Guarding is shown in Fig 8 where the output of the Device under Test is affected by a parallel path, or "Feedback Loop". If the DUT is not isolated from this parallel path during testing, erroneous test results may occur. Schematic generation Sometime may happen that we would like to have the schematic of the PCB we re testing. This is possible with the ICT which integrate Graphical editors for the schematic symbols and, after an optimized process of probing, generate the complete schematic of the UUT. Often this is a long process unless the ICT uses optimized algorithm to get the netlist and a quality schematic like the one we get from an EDA tool. VI or Signature Analysis This is a very popular option normally available in the ICT that do not require any test program to work. The Signature Analysis, or VI is a technique that inject a Waveform, generally a Sinewave, with limited current, onto a circuit node, or test point, on the KGB (Known Good Board). Then by monitoring both the Voltage Responses and the Current Responses from the particular node, a Lissajous figure can be plotted.this figure can then be compared with the one coming from the UUT. The VI Signatue is often very useful during the screening of the UUT. With this technique it s possible to inspect the boards and comparing the signatures coming from the same test point. 9

10 In practical even when the KGB is not available is, sometimes, still possible to test the board just looking for Open or Shorts on some specific components. In fact when the UUT have multiple channels, like an electronic Mixer for example, then the board can be tested comparing each channel with the other on the same board. VI is very flexible but of course there are some limitations on finding faults. First of all we need a KGB to learn the good signatures from. If this is not available then the use of VI can be restricted to test passive component out-circuit. For example we can measure capacitance and inductance of capacitors and coils since the VI works with programmable Voltage, frequency and waveforms. Other than this we can of course test resistors and all types of semiconductors. Zeners for example can be tested for the working voltage having the typical response displayed on screen. Zener reverse polarization A limitation that comes with the VI is that this method can be used to find the AREA of fault while the functional test point directly to the faulty device. 10

11 To clarify this, consider the following schematic : Suppose we probe to pin13 of U3.d and we find a different signature, then this can happen for at least three reasons: U4.d ouput is faulty, U3.a pin2 is faulty or U3.d pin13 is faulty. If others devices are connected to the same Net then we should consider their influence too. Boundary Scan An advanced ICT should be able to test devices with the JTAG standard known also as Boundary Scan Test. In this case the device will have some additional pins (JTAG pins) that allow a serial pattern to flow in a shift register behind each pin. This way we can program each pin as 1 or 0 and read back the same pattern. The BST uses 5 wires connected from the UUT to the ICT and can detect open and shorts on each pin of the device. It should be noticed that the BST is not a functional test. For example we could use it to test a BGA to verify if some pins are open or shorted but the internal functionality of the BGA can not be tested with the BST. BST can be used in production to find shorts and opens for example after the pick & place machine. Again a TI have to be provided by the TestEngineer after evaluation of the UUT schematics. In fact the TI depend on how many JTAG-devices are present on the chain and how many clusters. Many industries use mostly the AOI in production line. The JTAG standard IEEE today is widely used to program devices on-board (ISP). 11

12 AOI : (non functional test) The Automatic Optical Inspection is today used mostly in production after the pick and place machine where the time to test should be minimized. These ATEs uses Scanners or Cameras and can automatically identify solder defects, missing or wrong components, orientations, open, shorts and more The user have to program the UUT just once marking the components to be tested. Then while the UUT pass the AOI scan all the parts and identify possible defects very quickly. The main advantage of the AOI compared with with the BST is that it s more easy to use, can cover much more defects and is faster. Glossary AOI : Automated Optical Inspection ATE: Automatic Test Equipment BST: Boundary Scan Test Clusters : non JTAG components DMM: Digital Multi Meter Drive: The signal generated by the ICT DSO: Digital Storage Oscilloscope EDA: Electronic Design Automation FCT: frequency and Counter Timer GUI : Graphical User Interface ICE: In Circuit Emulator ICT: In Circuit Tester, a specific ATE ISP : In System Programmable JTAG : Join Test Action Group KGB: Known Good Board LSA: Logic State Analyser LSB: Less Significative Byte/Bit MSB: More Significative Byte/Bit Pad: the area of copper where the pin of the device contact the PCB. Can be SMT or Thru-Hole. Pattern: typically a sequence of logic zero and one. PCB : Printed Circuit Board PLD : Programmable Logic Device Sense: The signal measured by the ICT SMT: Surface Mount Technology SRAM: Static RAM Test vector: a sequence of logic zero and one that can also include analog measurements TI: Testability Index UUT: Unit Under Test, can be a device, a PCB or a system Alex Manfredini - Canarie International Copyright 2002, all rights reserved 12