FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers

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1 FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers Rene Griessl, Meysam Peykanu, Lennart Tigges, Jens Hagemeyer, Mario Porrmann Center of Excellence Cognitive Interaction Technology Bielefeld University, Germany

2 Motivation Rising demand for computing power Complexity of calculations Increasing number of users Energy consumption is rising 15 % of electrical energy consumption by computers CO 2 emissions Systems have to be cooled Complexity/Cost rising Integrate FPGA / ARM Founded by EC 2

3 Developing Hardware and Design Methodologies for Heterogeneous Low Power Field Programmable Servers 3

4 FiPS Achievements 4 Modular heterogeneous server system and middleware Up to 72 microservers in a single 1 RU server Supports x86/arm CPUs, GPGPUs, and FPGAs OpenCL runtime for FPGA modules 4

5 RECS Box Microserver Overview Apalis-based microservers COM Express-based microservers Microservers based on ARM- SoCs ranging from Cortex-A9 to Cortex-A15 Xilinx Zynq-based microserver x86 microservers ranging from Atom single cores to i7 quad core FPGA-based COM Express microserver, integrating Xilinx Zynq SoC 5

6 RECS Box Microserver Zynq COM Express Module Zynq 7045, ARM Cortex A9 Dual Core, 1 GHz Tightly integrated Programmable Logic Memory interfaces 1 GByte DDR3 (32-bit) PS Memory Up to 8 GByte DDR3 SO-DIMM module (64-bit-wide) PL Memory emmc memory (16 GByte) Secure Digital (SD) card slot All COM Express interfaces PCIe, Gigabit Ethernet, USB, DP, SATA, CAN, High-Speed Serial Links (dedicated connector) Up to 8 lanes, 12.5 Gbit/s each Crosspoint switch for network reconfiguration Expansion piggyback (e.g. for I/O, Accelerators) 6

7 Zynq 7020, ARM Cortex A9 Dual Core, 866 MHz Memory RECS Box Microserver Zynq Apalis Module 1 GByte of DDR3 (32-bit) PS Memory emmc memory (16 GByte) Secure Digital (SD) card slot Apalis Module Interface Compatible with Toradex Apalis standard (ETH, USB, HDMI, CAN, SPI, Camera, ) 2 Gigabit Ethernet interfaces 7

8 Benchmarking ANN for Minecraft Computation of Non Player Character (NPC) behavior in Minecraft FPGA-based neural network implementation for AI acceleration >100x performance improvement x86-server Environment Simulation AI FPGA ANN Communication 8

9 Benchmarking DNA Sequence Alignment CPU: Single-treaded implementation in C++ GPU: Implementation using CUDA FPGA: Implementation using High Level Synthesis 9

10 Modular Microserver Data Centre 10

11 M2DC Concept Flexible and scalable architecture Low power microserver nodes (ARMv8) Built-in acceleration (incl. FPGA-based microservers) Intelligent power management Built-in enhancements for perfomance, efficiency and security Easy to integrate with data centre ecosystems Tailored to specific real-life applications 11

12 M2DC Appliances Photo processing Scalable photo finishing for leading online photo service IoT data analytics Analysis of data from large numbers of sensors, e.g., for insurance companies Cloud computing Enhanced IaaS, PaaS solutions exploiting heterogeneity HPC Efficient meteorological simulations, used for predicting energy production 12

13 M2DC Server Architecture Architectural improvements focusing on communication 10 GbE Network PCIe switching High-Speed Serial Communication Scalable across rack level New Microservers 64-bit ARM Server Processors / SoCs Altera Stratix 10 SoC FPGAs 13

14 M2DC Server Architecture Communication infrastructure ikvm/ipmi to every microserver, including fine-grained, high-speed monitoring Baseboard Baseboard Microserver BaseboardModule Microserver Module Microserver Module CPU Mem I/O CPU Mem I/O 3/16 Microservers per Baseboard CPU Mem I/O Distributed Monitoring and KVM Up to 15 Baseboards per Server Backplane Distributed Monitoring and KVM 15

15 M2DC Server Architecture Communication infrastructure 1/10 Gbit Ethernet management 10/40 Gbit Ethernet compute Baseboard Baseboard Microserver BaseboardModule Microserver Module Microserver Module CPU Mem I/O CPU Mem I/O 3/16 Microservers per Baseboard CPU Mem I/O Distributed Monitoring and KVM GbE Compute Network Up to 15 Baseboards per Server Distributed Monitoring and KVM GbE Compute Network Backplane 16

16 M2DC Server Architecture Communication infrastructure > 50 Gbit, low latency communication infrastructure Possibility to integrate storage and PCIe-based extension cards Baseboard Baseboard Microserver BaseboardModule Microserver Module Microserver Module CPU Mem I/O CPU Mem I/O 3/16 Microservers per Baseboard CPU Mem I/O Distributed Monitoring and KVM GbE Compute Network Crosspoint- Storage / I/O-Ext. Up to 15 Baseboards per Server Distributed Monitoring and KVM GbE Compute Network Crosspoint- Backplane 17

17 Summary FiPS Field Programmable Servers RECS Resource Efficient Cluster Server Integration of CPUs, embedded/mobile CPUs, GPGPUs and FPGAs Evaluation using DNA sequencing HLS FPGA implementation provides maximum energy efficiency M2DC Modular Microserver Data Centre Architectural improvements focusing on communication New Microservers (64-bit ARM, Stratix 10 SoC) Large scale testbeds / applications 20

18 Many Thanks! René Griessl Cognitronics and Sensor Systems Center of Excellence Cognitive Interaction Technology Bielefeld University, Germany