Introduction to Integrated Flash Controller and a Comparison with Enhanced Local Bus Controller

Transcription

1 Introduction to Integrated Flash Controller and a Comparison with Enhanced Local Bus Controller FTF-NET-F0151 Ram Gudemaranahalli Applications Engineer A P R TM External Use

2 Session Introduction This session provides an introduction to the Integrated Flash Controller (IFC) and the different sub controllers within it. It also provides a brief comparison with the older enhanced Local Bus Controller (elbc) to highlight the different merits that IFC has. External Use 1

3 Session Objectives After completing this session you will be able to: Understand the purpose of IFC Be able to understand different controllers within IFC Understand how to interface IFC with different types of flash memories Compare merits and demerits of IFC with respect to elbc External Use 2

4 Agenda Introduction to Integrated Flash Controller (IFC) Differences between IFC and elbc (enhanced Local Bus Controller) NOR controller NAND controller GPCM controller Normal GPCM GASIC controller External Use 3

5 Usage of Integrated Flash Controller (IFC) Role of IFC After the power is turned on, a typical system: Starts execution from non-volatile memory, typically NOR/NAND flash memory Copies the code to main memory (DDRx) Starts the execution from main memory Core U-boot/ BIOS Flash Storage ROM/Hard Drive Main Memory DDRx External Use 4

6 Initial Boot A system must be able to talk to non-volatile memory without any software configuration steps Integrated Flash Controller does this initial booting job with two controllers: NOR controller Standard and page mode NOR flash Support booting NAND flash control machine (FCM) NAND memory for storage Support booting GPCM Normal GPCM: memory addressed devices, standard NOR flash, SRAM, ROM, FPGA Generic ASIC: FPGA No booting External Use 5

7 IFC Versions Currently three major versions of IFC: rev 1.0, rev 1.1 and rev 2.0 How to know the version number IFC revision control register (IFC_REV), offset 0x0 Some improvements in rev rev2.0 Synchronous NOR support. Improved NAND SRAM size and 16KB page support Internal DMA IFC is little endian IFC Usage: IFC1.0: P1010, P2021 IFC 1.1: B9164,B3241, T4240, P1040., P2022, T1040, T2080, LS1020a Rev 2.0: To be announced External Use 6

8 IFC, elbc Comparison Machine Features IFC elbc Devices max page size Error correction per sector Flexible timing control allows interfacing with proprietary NAND IFC rev1.0: 4KB IFC rev1.1: 8KB IFC rev 2.0: 16KB IFC rev1.0: 4-bit, 8-bit/512Byte IFC rev1.1: 4-bit, 8-bit/512Byte 24-bit, 40-bit/1Kbyte Yes 2KB 1-bit /512Bytes Limited capability NAND Flash Provide cache, copy-back and multi-plane command support Programmable command and data transfer sequences BBI page position Configurable block size constraint to multiple of 32 pages, up to 2048 pages Yes No Up to 15 Up to 8 Configurable between (second and last page) First two pages of each block Internal SRAM size 9KB, 18KB(Rev2.0) 5KB Max initial boot code size for NAND flash 8KB,16KB(Rev 2.0) 4KB Yes No SRAM parallelism Not-Allowed Allowed External Use 7

9 IFC, elbc Comparison (continued) Machine Features IFC elbc Compatible with page mode NOR flash Yes No Support True-Address/Data-Muxed devices //recheck Yes No NOR Flash Flexible timing control allows interfacing with variety of NOR devices Yes Limited capability Synchronous NOR support Yes(Rev2.0) No Other GPCM Yes (with enhanced timing control) UPM No Yes Yes GASIC Yes No External Use 8

10 Interface Signals Name IFC elbc Address/Data IFC_AD LAD Address IFC_ADDR LA Address Valid IFC_AVD LALE/LFALE Chip Select IFC_CS_B LCS Write Enable IFC_WE_B LWE_B Command Latch Enable IFC_CLE LFCLE Output Enable IFC_OE_B LOE_B Write Protect IFC_WP_B LFWP_B Ready/Busy IFC_RB_B/IFCTA_B LFRB_B Buffer Control IFC_BCTL LBCTL Parity IFC_PAR[0:3] LDP[0:1] Parity Error IFC_PERR Not Available Clock IFC_CLK LCLK External Use 9

11 NOR Flash Control Machine External Use 10

12 Performance NOR Controller Support standard asynchronous NOR flash and synchronous NOR flash(rev 2.0) Support page mode NOR flash NOR Flash Type No support for synchronous burst mode NOR flash Burst Mode Supports address data multiplexed AVD-type NOR device Data bus width of 8/16/32 Standard Page Mode Complexity External Use 11

13 Page Mode Flash Standard NOR flash vs. Page Mode NOR tacc = 100 ns, tpacc = 25ns For 16-bit interface and a 32-byte cache line read Standard flash: 100ns x 16 = 1600 ns Page mode: 100ns + 15*25ns= 475ns #Denotes logic low signal External Use 12

14 Two Types of NOR Flash Non-AVD Regular NOR Flash Address is driven before CE# Set CSORn[NOR_MODE]=0 AVD NOR Flash Address is driven along with AVD# Set CSORn[NOR_MODE]=1 #Denotes logic low signal External Use 13

15 Interfacing IFC Non-AVD Regular 16 bit NOR Flash IFC NOR Flash IFC_AD[0:15] IFC_AD[0:15] latch latch_addr[0:15] DQ[15:0] A[23:8] IFC_ADDR[16:23] IFC_ADDR[24] x A[7:0] IFC_AVD IFC_OE# IFC_WE# IFC_CS# IFC_WP# AVD# OE# WE# CE# WP# HRESET NC RST# WAIT CLK P1010 GND #Denotes logic low signal External Use 14

16 Interfacing IFC AVD-type 16 bit NOR Flash IFC NOR Flash IFC_AD[0:15] IFC_ADDR[16:23] IFC_AD[0:15] IFC_ADDR[16:23] DQ[15:0] A[23:8] A[7:0] IFC_AVD IFC_OE# IFC_WE# IFC_CS# IFC_WP# AVD# OE# WE# CE# WP# HRESET NC RST# WAIT CLK P1010 #Denotes logic low signal GND External Use 15

17 Key Points in NOR Setup External latch is not needed for AVD NOR flash For non-avd NOR flash, address latch is needed After power on reset, CSORn[PGRD_EN] is set to 0 Software must set this bit to enable page read mode When choosing page-mode flash, page size must be same as cache line (ie: 32 bytes) Take advantage of page mode Use DMA to copy code from NOR flash to DDR Enable cache External Use 16

18 NAND Flash Control Machine External Use 17

19 Overview of NAND Flash Higher-density / lower-cost than regular flash (NOR flash) IO device using commands to read/write No address bus Page-oriented, not suitable for random access Possible bit error Usually a certain number of blocks are marked bad by manufacturer During the operation, more blocks can go bad ECC is a must No execute in place (XIP) Long wait time for random address Possible bit error only known after whole page read and ECC check External Use 18

20 NAND Controller Features and Facts Support x8/x16 NAND devices ONFI (Open NAND Flash Interface) asynchronous interface with mandatory commands BCH coding for 4/8 bit error correction per block IFC rev1.1 adds support of 24-bit/1K, 40-bit/1K Page size: Support 512 bytes, 2K and 4K IFC rev1.1 adds support of 8K page IFC rev 2.0 adds support of 16K page Configurable block size, from 32 to 2048 pages per block External Use 19

21 SRAM Buffer SRAM Buffer System Bus NAND interface NAND devices 4K Due to the slowness of NAND devices, SRAM buffer is used to decouple the system bus from NAND accessing System bus read/write to the memory bank (defined by CSPR[BA]/AMASK[AM]) actually accesses SRAM For NAND write: (1) Data is transferred to SRAM. (2) Start NAND write with NANDSEQ_STRT; data transferred from SRAM to NAND During the write, SRAM must not be accessed For NAND read: (1) Start the NAND read with NANDSEQ_STRT; Data transferred from NAND to SRAM SRAM must not be accessed during the read operation (2) Core accesses data from SRAM External Use 20

22 How Does NAND Controller Work Different vendors might have slightly different sequences Commands might be different, especially for small page NAND FCM takes a generic approach: User has flexibility/responsibility to define command sequence based on NAND NAND controller also supports a few standard commands Programming model 1. Generate the command sequence 2. AC timing control External Use 21

23 How to Generate the Command Sequence Method1: NAND_FIR0-2 op0 op1 CA0 op2 RA0 op3 WBCD op4 op5 NOP op6 op7 op8 op9 op10 op11 op12 op13 op14 NAND_FIR0 NAND_FIR1 NAND_FIR2 cmd0 cmd1 cmd2 cmd3 cmd4 cmd5 cmd6 cmd7 CW0 NAND_FCR0 NAND_FCR1 CMD1 ONFI 2.2 Page Program Cycle type CMD CMD DQ 80h 10h Number of column address cycles depends on page size NAND_CSEL CSEL Select which CS MS IFC_COL0 CA External Use 22 Start the operation RA IFC_ROW0 NANDSEQ_STRT FIR_STRT Number of row address cycles depends on CSOR_NAND[RAL] BC NAND_BC Number of data cycles depends on NAND_BC BC=0 for whole page

24 NAND AC Timing Control NAND interface is asynchronous all the control and data signals have to maintain proper AC timing AC timing is defined in four registers IFC_FTIM0_CSn_NAND, IFC_FTIM1_CSn_NAND IFC_FTIM2_CSn_NAND, IFC_FTIM3_CSn_NAND External Use 23

25 AC Timing Control: Mapping Between ONFI Spec and IFC Registers ONFI AC Timing Parameter tadl tals, tcls, tds, twp talh, tclh, tdh, twh trp treh trr twb twc IFC control FTIM1_CSx[TADLE] FTIM0_CSx[TWP] IFC drives ALE/CLE/DQx at the falling edge of WE#. TWP > max{tals, tcls, tds, twp} FTIM0_CSx[TWCHT] IFC negates ALE/CLE/DQx at the same time after WE# high. TWCHT > max{talh, tclh, tdh} FTIM0_CSx[TWH] FTIM1_CSx[TRP] FTIM2_CSx[TREH] FTIM1_CSx[TRR] FTIM1_CSx[TWBE] TWH+TWP > twc External Use 24

26 AC Timing Control ONFI AC Timing Parameter trc tww tcs tch IFC Control TRP + TREH > trc FTIM3_CSx[TWW] Command latch cycle: Satisfied automatically during Data write cycle: FTIM0_CSx[TWH] > tch trhz trea twhr tir trhw CSORx_NAND[TRHZ] > trhz FTIM2_CSx[TRAD] Data sampling point trp-trea+trhoh FTIM2_CSx[TWHRE] Satisfied automatically since it is much smaller than twhr CSORx_NAND[TRHZ] > trhw External Use 25

27 Booting from NAND and Reset Configuration NAND controller is selected as the boot ROM location cfg_rcw_src example: 1_0000_00xx: 8-bit NAND Flash, 512-byte page, 32 pages/block 1_0000_01xx :8-bit NAND Flash, 2 KB page, 64 pages/block NAND controller searches for a valid boot block Reads data until 8K SRAM buffer is filled ECC errors are corrected if possible and enabled. Boot stops if error is uncorrectable, the device reset sequence is halted indefinitely until Poreset_b is asserted The CPU is released to start fetching instructions from the SRAM buffer External Use 26

28 Interfacing 8-bit NAND with P1010 Bit reversing External Use 27

29 Interfacing 16-bit NAND with P1010 For elbc For IFC Byte swapping Bit reversing External Use 28

30 GPCM External Use 29

31 GPCM Controller GPCM supports two modes: Normal GPCM Generic ASIC Enable GPCM and select mode CSPRn[MSEL]: 0b10 for GPCM CSORn[GPMODE]: 0 for normal GPCM, 1 for generic ASIC Normal GPCM is similar to elbc GPCM with new programming model Generic ASIC is a new function External Use 30

32 Normal GPCM Mode: Write Normal GPCM can be used to generate standard NOR flash interface compatible control signals ALE timing controlled by FTIM0_CSn TACSE: Address to CS assertion TEADC: Pulse width of ALE TEAHC: ALE to address hold time WE timing for read controlled by FTIM2_CSn TCS: CS to WE assertion time TWP: WE pulse width TCH: WE negation to CS negation GPCM Write External Use 31

33 Normal GPCM Mode: Read ALE timing controlled by FTIM0_CSn TACSE: Address to CS assertion TEADC: Pulse width of ALE TEAHC: ALE to address hold time OE timing for read controlled by FTIM1_CSn TACO: CS to OE time TRAD: OE pulse width GPCM Read External Use 32

34 Normal GPCM Mode: External Termination Option for external termination by IFCTA CSORn[RGETA], CSORn[WGETA] 0: Terminated by internal TRAD counter for read or TWP for write or IFCTA if it is asserted earlier than internal timer expiration 1: Only terminated by assertion of IFCTA, not internal timer This feature is useful if response time is variable External Use 33

35 Generic ASIC A simple interface useful for talking to FPGA IFC supports the following features on GASIC interface: Support for x8/16-bit device Address and data are shared on AD I/O bus; dedicated address pins are not used The following address and data sequences will be supported on I/O bus 16-bit I/O: AADD 8-bit I/O: AAAADDDD Configurable even/odd parity on address/data bus supported Parity error detection supported GASIC interface does not support: Boot from GASIC Burst transaction External Use 34

36 Generic ASIC: 16-bit Interface Read External Use 35

37 Generic ASIC: 16-bit Interface Write External Use 36

38 Unsupported Features GPCM Autoboot No machine interleaving Command based NOR flash External Use 37

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41 See the LS2 Family First in the Tech Lab! 4 new demos built on QorIQ LS2 processors: Performance Analysis Made Easy Leave the Packet Processing To Us Combining Ease of Use with Performance Tools for Every Step of Your Design External Use 40

42 Freescale Semiconductor, Inc. External Use

43 Backup slides Address shifting External Use 42

44 Multiplexed Bus Address and data are multiplexed in the same pins to reduce pin counts. LALE (Local bus Address Latch Enable): Indicates the address phase There are two main variations: 32-bit bus: LAD[0:31] LA[27:31] 16-bit bus: LAD[0:15] LA[16:31] lad[0:26] la[0:26] lad[0:15] la[0:15] lale latch la[0:31] lale latch la[0:31] la[27:31] la[16:31] Advantage: Higher performance Advantage: Fewer pins, narrower latch External Use 43

45 How FCM Operates Write data to NAND 1. Initialize FCM registers for write 2. Set FMR[OP]=00, normal operation Fill the buffer with the data 3. Set FMR[OP]=11 after the data (usually one whole page) is in the buffer 4. Dummy write to memory bank or write to LSOR to start the write sequence 5. FCM reads data from buffer, writes to NAND Core is free to access the other 4K buffer when FCM writes to NAND core OP=00 OP=11 data 0 data 1 4K data n 4K write to LSOR or dummy write data 0 data 1 data n Large Page NAND External Use 44

46 Freescale Semiconductor, Inc. External Use