A 6-Bit Multi-Resolution Digital to Analogue Converter for Low Temperature Poly-Silicon Digital Drivers

Transcription

1 Header for SPIE use A 6-Bit Multi-Resolution Digital to Analogue Converter for Low Temperature Poly-Silicon Digital Drivers Mike Brownlow a, Graham Cairns a, Catherine Dachs a, Y. Kubota b, H. Washio b, H. Yamashita b a Sharp Laboratories of Europe Ltd., Oxford, UK. b Liquid Crystal Laboratories, Sharp Corporation, Tenri, Japan. ABSTRACT A key requirement for the development of advanced digital drivers for Low Temperature Poly-Silicon (LTPS) active matrix displays is the provision of a high bandwidth, high resolution Digital to Analogue Converter (DAC) as a prerequisite for higher level integration. For a given panel specification and data rate, the bandwidth and resolution of the conversion process directly influence the efficiency of a digital driver implementation in terms of bezel size, transistor count and power consumption. This paper is concerned with the design and realization of a programmable high performance DAC architecture which meets the requirements for a compact and highly efficient digital data driver. The high performance of the two-stage architecture is achieved by means of a novel pre-charge arrangement that not only increases the speed of operation, but also provides for offset compensation of an analogue buffer with considerably reduced slew rate requirements and power consumption. A switched capacitor implementation of the DAC architecture is presented and the theoretical specifications are verified by simulation. The application of the new architecture to advanced digital drivers with programmable input data resolution is briefly discussed. Keywords: Digital to Analogue Conversion, DAC, Digital drivers, Poly-Silicon, TFT LCD 1. INTRODUCTION The increasing use of Low Temperature Poly-Silicon displays for mobile multi media devices such as personal AV products and PDAs shows every sign of continuing. The most important reason for this trend has been the high resolution and therefore excellent display quality that is afforded by monolithic driver integration. To date, most Poly-Silicon displays have used analogue monolithic drivers based on the panel-sample-and-hold architecture, in which a spatially distributed shift register and sampling circuits sequentially sample an analogue video input onto the active matrix. This approach has the advantage that the on-panel circuitry is kept to a minimum, and so it is relatively straightforward to implement with moderate performance poly-silicon TFTs and large area lithography. However, this simple architecture requires a considerable amount of external support circuitry to interface the display with the application. The external support circuitry, which typically includes a video controller, digital to analogue converters and voltage level-shifters not only takes up space, but also consumes significant power. Another key growth area for high resolution displays is in the next generation of mobile communication devices, although in these products a greater emphasis is placed on low cost and low power consumption. Currently this market is dominated by colour STN displays which have unrivalled power consumption figures and can be fabricated on lightweight flexible substrates. Nevertheless, their performance is expected to fall short of supporting third generation applications such as videophones with integral cameras. Already makers of prototypes for these products have turned to active matrix technology. In anticipation of this, recent developments in amorphous-silicon TFT technology have seen the emergence of very high-resolution displays based on Ultra High Aperture (UHA) technology, with conventional low voltage IC drivers optimized for low power consumption. For Poly-Silicon displays to be competitive in these markets they must offer not only high resolution, but are also required to challenge the other specifications of display performance, such as system interface compatibility, power consumption, bezel size and cost. Meeting this challenge requires significantly improved performance from the monolithic circuitry

2 together with high performance processes. This paper is primarily concerned with the first objective, namely improving the performance of the monolithic circuitry. Several Poly-Silicon displays have included monolithic digital drivers to simplify the external interface by taking the input data for the display in digital format and performing the conversion to analogue voltages on panel. To date, however, the relatively low performance of the monolithic Digital to Analogue Converters (DACs) within the drivers has often resulted in displays that generally require larger bezel sizes and significantly increased power consumption compared to their analogue counterparts. The development of a high bandwidth, high resolution converter is therefore of key importance for poly- Silicon displays to meet all the specifications for mobile multi-media applications. In the next section we present a brief overview of how the speed of conversion and drive capability of the DAC affect the overall architecture and efficiency of monolithic digital drivers. In section 3 we present a new high speed DAC architecture and describe the operation. In section 4 we present the simulation results which confirm the high performance of the converter. The paper concludes with an overall assessment of performance and a discussion on the application of the new DAC to advanced digital drivers which will be reported at a future date. 2. IMPROVING DAC PERFORMANCE: SIMPLIFYING THE DIGITAL DRIVER Monolithic digital data drivers are considerably more complex than analogue drivers. Their design represents a significant challenge due to the relatively poor performance of thin film transistors compared to single-crystal Silicon, and the low integration density afforded by large-area lithography. In a typical digital driver for an N row by M column active matrix operating at a frame rate F, the N rows of parallel k-bit RGB input data are transmitted serially at a frequency FNM. Each row of data is supplied within a period 1/FN, defined by the horizontal synchronization pulses, as shown in Figure 1. One horizontal line-time Column 1 Column M HSYNC k-bit input data R(0:k-1) G(0:k-1) B(0:k-1) Figure 1: Timing diagram for a typical digital data driver The role of the digital driver is to convert the serial digital data into parallel analogue format for driving the M columns or data lines of the active matrix, under control of the data clock and horizontal synchronization signals. The conversion of the video rate digital data into analogue voltages with sufficient drive capability to charge the highly capacitive data lines according to the timing diagram of figure 1, is a key function of the driver. Other driver functions such as distributed high speed timing and low voltage interface technology are described in a previous publication 1. For a given accuracy and load capacitance, the speed of conversion of the Digital to Analogue Converter (DAC), T CONV, compared to the input data period 1/FNM, has a very great influence on the overall architecture and area efficiency of the driver. The speed of conversion depends on the DAC architecture, which sets the internal conversion time, and whether it is buffered to reduce the output impedance and increase the drive capability. High performance buffered DACs have not received widespread attention for poly-silicon due to the inherent problems of process variation on analogue buffer performance, although simple single stage buffers have been proposed for driving data lines 2. Non-buffered DACs, however, which rely on the resistive or capacitive conversion elements to drive the load directly, have been widely used despite the considerably longer conversion times for large load capacitance.

3 Timing Digital input data Shift register Input register Storage register 1 low performance DAC / column Active Matrix C S Figure 2: Typical driver architecture based on low performance DACs Since the conversion time for non-buffered DACs is generally very much greater than the data period 1/FNM, many DAC circuits are required to operate in parallel to achieve the required throughput. Figure 2 shows a typical digital data driver architecture based on this constraint, using non-buffered binary-weighted capacitor DACs 3. In this architecture, the driver samples the digital data for the current line, whilst simultaneously converting the previous line of data from digital to analogue format. The digital storage provides a pipeline delay of one line-time, 1/FN, in which the non-buffered DACs can drive the columns of the display. The overhead on the digital circuitry is very severe, however, with two full lines (2M) of k-bit RGB storage required, together with M DAC circuits. This approach often results in large double-sided drivers, and may result in reduced panel yield. The situation can be improved somewhat by multiplexing the DAC circuits and increasing the speed of conversion, so that each DAC can drive more than one data line. The drive capability of standard DAC architectures is only sufficient to drive columns which are local to the DAC circuit, which implies that the digital storage cannot be multiplexed without re-ordering the input data and thereby complicating the interface. High performance global DACs Multi-phase analogue video lines Timing Digital input data C V Conventional multi-phase analogue driver Active Matrix CS Figure 3: Highly simplified architecture based on high performance buffered DACs If the conversion speed is comparable to the data period then it is attractive to consider a highly multiplexed architecture 4, requiring a small number of very high-speed DACs with high drive capability as illustrated in Figure 3. The digital input data is sampled and stored locally, prior to conversion into a small number of analogue video phases, which are distributed across the panel. A standard multi-phase analogue driver performs the spatial sampling onto the data lines of the active matrix. Since the digital storage is minimized, this architecture requires considerably fewer transistors and is much more compact. In fact, the principle of operation is very similar to the off-panel electronics that support conventional multi-phase analogue drivers. This highly multiplexed approach is only possible if the DACs are capable of charging the very considerable capacitance presented by the cross-panel video lines, C V and the selected data lines, C S. The combined

4 capacitance can be more than an order of magnitude larger than the data line capacitance alone, and hence a special DAC architecture is required. To place design constraints on the level of performance required, consider a typical 2 QVGA display specification for mobile applications. In this case the video rate is approximately 6MHz and the load capacitance will be of the order of 50pF. A single-phase architecture would have to perform the high resolution DAC operation and charge the 50pF load in 166ns, whilst a six phase system would require a 1us conversion time. The design challenge, therefore, is to devise a DAC architecture for low temperature poly-silicon digital drivers, which can perform 6-bit conversion and gamma correction in less than 1us, whilst driving a capacitive load of approximately 50pF. The design of this new architecture is presented in the next section 3.1 Overview 3. THE NEW DAC ARCHITECTURE The architecture for a new high performance digital to analogue converter is shown in Figure 4. The new architecture facilitates programmable multi-resolution operation and is capable of high speed conversion into large capacitive loads. 6-bit digital data Voltage references VR(0:9) Voltage reference selector Input data register 6 bit data 3 bit LSBs VH V L 3-bit LSB DAC Buffer Power control Isolation switch SW2 Offset compensation CLOAD Pre-charge switch SW1 Resolution control signals Convert clock 3B 1B Resolution control register Timing & control Figure 4: Block diagram of the architecture for a new digital to analogue converter The converter can be conveniently partitioned into the following functional units: Resolution control register: stores a 2-bit resolution control word for selecting one of three conversion modes. Data register: provides temporary storage for the 6-bit digital input word during the conversion process. Two-stage non-linear conversion core: performs gamma correction according to the input data and conversion mode. Pre-charge system: charges the load in two steps to significantly improve conversion speed. Analogue buffer: provides a low impedance drive capability for 6-bit mode. Offset compensation network: removes the voltage offset of the buffer due to process variations. Timing generator: generates two phase non-overlapping clocks and control signals for the converter.

5 3.2 Principle of operation The mode of operation of the converter is controlled by the contents of the resolution control register. This is a key innovation for multi-format displays, since the power consumption of the converter can be optimized according to the resolution of the input data 4. Three different conversion modes can be selected by means of the resolution control signals, 3B and 1B. These modes are full 6-bit resolution, 3-bit resolution or 1-bit (binary) resolution. The state of the resolution control signals for each mode of operation is shown in Table 1. Resolution control signals Conversion mode Characteristics 1B 3B bit High colour resolution, highest power bit Intermediate resolution and power bit Binary operation, very low power Table 1: Multi-resolution control signals and the characteristics of each conversion mode. Since the detailed operation of the converter depends on the selected mode, the description of the converter will begin with the full 6-bit mode. Modifications to the basic operation for the simpler reduced resolution modes will then be highlighted. Transmission (%) VRB (special case for ) reference voltages normalized LC transmission VR0 Voltage (V) VR1 VR2 VR3 VR4 VR5 VR6 VR7 1.0 VR bit digital input Figure 5: Two-stage conversion and gamma correction 3.3 Gamma correction Gamma correction of liquid crystal displays involves compensating for the pixel non-linear voltage / light modulation characteristic, so that equal changes in digital input correspond to equal changes in light transmission. The smooth curve in Figure 5 shows a typical normalized LC transmission curve, with percentage light transmission plotted on the upper x-axis, against applied voltage on the y-axis. In order to implement this non-linear transfer characteristic as accurately as possible, the converter uses a two-stage operation to perform a piece-wise linear approximation between externally supplied reference voltages. A detailed view of the converter core is shown in Figure 6. The first stage of the converter operates primarily on

6 the 3 most significant bits (MSBs) of the 6-bit input, and the second stage receives the remaining 3 least significant bits (LSBs). The MSBs are decoded into one of eight sub-ranges, the end points of which are defined by selecting a consecutive pair of reference voltages, V H and V L, from VR 0 to VR 8. The selected reference voltages are passed to the second stage DAC, where the 3 LSBs are used to perform a linear conversion between the limits defined by V H and V L. The second stage of the converter is a binary-weighted parallel capacitor array that is connected to the input of the analogue buffer for driving the highly capacitive cross-panel video lines. In order to improve the contrast ratio, a special case reference VR B is explicitly decoded by a signal, SB, when the input is This special case reference is supplied directly to the precharge circuit, which is now described. D 0 -D 5 Reference selector 1B 3B LSB C-DAC DECODER 1-bit mode bit mode bit mode xxx 001xxx 010xxx 011xxx 100xxx 101xxx 110xxx 111xxx SB V H Φ 1. D 0 C Φ 2 +!D 0 V L Φ 1. D 1 2C Φ 2 +!D 1 Φ 1. D 2 4C To Buffer Φ 2 +!D 2 VR 8 VR 7 VR 6 VR 5 VR 4 VR 3 VR 2 VR 1 VR 0 VR B Figure 6: Two-stage converter core To Pre-charge 3.4 Pre-charge circuit The two stage nature of the piece-wise linear approximation offers a very convenient means to improve the speed of the conversion process in 6-bit mode by charging the output load with the intermediate result of the MSB conversion, prior to completing the LSB conversion. This technique not only speeds up the process, but also significantly reduces the large signal slew-rate requirements and power consumption of the buffer. The timing generator shown in Figure 7, controls this operation. If the control signals 1B, 3B and SB are all zero, i.e. 6-bit mode is selected and the special reference VR B has not been decoded, then the conversion control clock CONV is converted into two non-overlapping clock phases Φ 1 and Φ 2. If, on the other hand, any of the control signals are high, then Φ 2 is inhibited and Φ 1 is high for the entire conversion period. Referring to Figure 6, the two phases Φ 1 and Φ 2 control the precharge switch, the buffer isolation switch and the buffer offset-voltage compensation network. During Φ 1, the video line is charged through the pre-charge switch SW 1 to the intermediate 3-bit MSB DAC voltage V L. At the same time, the C-DAC capacitors are also charged to V H, conditional on the relevant bits being set, and the offset voltage of the buffer is measured. The charging of the video line capacitance during Φ 1 ensures that the voltage on the load capacitor is approximately within 3 LSBs of the desired final result. During Φ 2, the capacitors in the LSB CDAC are connected to V L, the buffer offset is subtracted and the output is charged by the buffer to the final value via the isolation switch SW 2. For the special case , SB is high which inhibits Φ 2 so that the load is charged accurately to VR B for the entire conversion period through the pre-charge switch SW 1.

7 Resolution control signals CONV!3B!1B!SB Special case reference decoded Φ 1 Φ 2 Figure 7: Pre-charge control logic Figure 8 shows a comparison of the conversion speed of a conventional single phase converter shown on the left, with the new pre-charge approach shown on the right, for the same buffer slew rate, S. From this figure it is clear that pre-charge technique reduces the slew rate requirements by approximately an order of magnitude for a given conversion speed. Furthermore, the explicit decoding of VR B considerably reduces the output swing of the buffer. These factors together make the design of the buffer for low temperature poly-silicon a tractable proposition. V H V L Target 6 bit conversion result Small signal settling time V H V L Target 6 bit conversion result Φ 1 : Pre-charge to MSB value via SW1 Φ 2 : Buffer drives LSB range only V C(0) Buffer slew-rate, S V C(0) DAC conversion period Φ 1 Φ 2 DAC conversion period Figure 8: Improved two-stage conversion (right) with pre-charge to intermediate MSB result The operation for 3-bit and 1-bit modes follows directly from the above description. Since either 1B or 3B are active in these modes, the control circuit inhibits Φ 2 and also the power supplies to the buffer, the LSB DAC and relevant digital storage registers. The voltage selector outputs a subset of the relevant voltage references, as indicated in Figure 6, and V L charges the video line for the entire conversion period directly through the pre-charge switch SW 1.

8 3.5 Analogue Buffer A block diagram of the analogue buffer with offset compensation is shown in Figure 9. As described previously, the precharge technique considerably reduces the requirements of the buffer. Nevertheless, for maximum performance, the following specifications must be considered: Bipolar output capability with respect to the liquid crystal counter plate voltage, V COM. Robustness to variations in process parameters, with minimal offset voltage. Low quiescent power consumption, sufficient drive capability and high speed. Process tolerant operational amplifier No CMR limitations Differential input stage Coupling network Class AB output stage Isolation switch SW 2 V COM - + Φ 2 C DAC Input referred offset voltage VOS C C Φ 1 Dynamic frequency compensation C LOAD Φ 1 C F Offset compensation network Φ2 V L Φ 1 Φ 1,2 Figure 9: Architecture for a process tolerant analogue buffer with offset compensation The operational amplifier is used in the inverting configuration, with the 3-bit binary weighted C-DAC capacitor array connected directly to the inverting input, and the non-inverting input held at a constant bias voltage, conveniently equal to the counter plate voltage of the liquid crystal panel, Vcom. Since both input terminals remain at a substantially constant voltage there are no common mode range (CMR) problems as there are with the more conventional non-inverting voltage follower configuration. This simplifies the design of the differential input stage, and provides a degree of robustness to large threshold voltages to ensure that all transistors remain in saturation. Since there are no CMR limitations, the output of the amplifier is able to swing symmetrically about the VCOM bias voltage all the way to each power supply rail. One of the most important properties of a buffer is termed the input referred offset voltage. For a properly designed amplifier with no systematic offset, the main cause of voltage offset error is due to mismatches in the parameters of the transistors in the circuit - particularly the threshold voltage. In a typical single crystal CMOS IC, the random offset voltage is of the order of several mv, and can be improved by layout techniques with matched devices in close proximity to each other. For poly-silicon, however, the story is very different and adjacent TFTs can have a random threshold voltage difference of several hundred mv as a result of the individual crystal structure of each transistor. To achieve the few mv accuracy required for driving the liquid crystal display it is necessary to design a buffer with an automatic offset compensation system. The offset compensation network that we have implemented operates on the two non-overlapping clock phases Φ 1 and Φ 2. During Φ 1 the amplifier is configured as a voltage follower with a constant input voltage V COM and

9 the output voltage, including the random offset, is measured and stored across the capacitor C F. During Φ 2, capacitor C F is connected between the output and the inverting input terminals of the operational amplifier thus subtracting the offset voltage by negative feedback. Since the inverting input terminal remains at a substantially constant potential, the effects of charge sharing between the CDAC and parasitic capacitance at the amplifier input are greatly minimized. This allows relatively wide input transistors to be used in the amplifier to achieve closer initial matching of the threshold voltages, without introducing error. The internal architecture for the amplifier itself is based on a differential input stage and a class AB output stage. The class AB output stage provides high drive capability without consuming excess quiescent current and the differential input stage operates under constant bias conditions. The coupling between the stages and the internal biasing circuits are designed to ensure that the operating point of the amplifier is reasonably insensitive to wide variations in the process parameters. Dynamic frequency compensation is used to increase the slew rate of the amplifier by exploiting the different load characteristics seen at the amplifier output in each of the two clock phases. The two-stage amplifier is in the most unstable configuration during the offset measurement phase, Φ 1, since it is configured as a voltage follower with 100% negative feedback. However, in this condition the load capacitance is also minimal since the switch SW 2 isolates the video line capacitance form the amplifier output. During clock phase, Φ 2, the situation is reversed and the amplifier is connected to very large load capacitor, but at the same time extra stability is provided by the integrating action of the offset compensation capacitor C F. Switching in different inter-stage compensation networks for each phase of operation allows the frequency response of the operational amplifier to be tailored towards optimum performance in each configuration. This technique allows the output of the amplifier to rapidly slew to the voltage level on the pre-charged video-line, whilst ensuring sufficient phase margin during offset compensation. 4. SIMULATED RESULTS The new DAC has been successfully simulated and Figure 10 shows the layout of the DAC, highlighting the main functional components. 2.0mm Data register Timing Decoder & resolution control Voltage References MSB Voltage selector & pre-charge LSB C-DAC Analogue buffer Figure 10: Layout of the new DAC

10 The performance figures for the DAC are summarized in Table 2. Key points to note are the 1us conversion time into a 100pF load, low power consumption of only 3.5mW at 12V power supply and sufficient accuracy for 6-bit operation. Specification Value Conditions Power supply, Vdd 12V DC Bias voltage, V COM 6V DC Voltage references V COM +/- 4.5 V COM +/ values, supplied externally DAC Resolution 6-bit, 3-bit, 1-bit Programmable, 3 modes DAC linearity < ½ LSB 6-bit mode, VH-VL =0.8V DAC conversion time 1us 100pF load Buffer settling time 200nS 100pF load, full LSB range Buffer output range 2V 10V Vdd = 12V Buffer power consumption 3.5mW Vdd=12V Table 2: Specifications for the new DAC 5. CONCLUSIONS We have presented a new high performance DAC architecture which is suitable for application to advanced poly-silicon displays which can meet the demanding specifications of next generation mobile products. A key innovation of the new DAC architecture is the facility for programmable resolution control as a means to optimize the power consumption according to the bit-resolution of the input data. The high performance of the DAC is achieved by means of a novel precharge arrangement which not only increases the speed of conversion, but also reduces the slew rate and power consumption of an analogue buffer with offset compensation. The application of the programmable DAC architecture to multi-format digital displays will be reported in the future 4. ACKNOWLEDGEMENTS The authors would like to thank the many members of Liquid Crystal Display Laboratories (SHARP Corporation) who have contributed to and supported this work. REFERENCES 1. G. Cairns, et al., High performance Circuitry for Poly-Silicon Integrated Drivers Euro Display 99 pp S. W. Lee, et al., High Performance Low Power Integrated 8-bit Digital Data for Poly-Si, SID 99 Digest, pp Y. Matsueda, et al., A 6-bit Color VGA LTPS TFT LCD with Integrated Digital Drivers, SID 98 Digest, pp G. Cairns, et al., Multi-Format Digital Display with Content Driven Display Format, SID 01 Digest, pp. TBA