Exercise 1: Static Control of a Data Bus

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Exercise 1: Static Control of a Data Bus EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the function of the CS signal and R/W signal in controlling data

1 Exercise 1: Static Control of a Data Bus EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the function of the CS signal and R/W signal in controlling data transfer by using the DATA BUS CONTROL circuit block. You will verify your results by observing the logic states of control and data lines. EXERCISE DISCUSSION In the DATA BUS CONTROL circuit block, the data bus between a CPU and an I/O device is labeled CPU BUS. The inverter, the WRITE and READ AND gates, and the WRITE and READ tri-state buffers are part of the I/O device. The labels DATA OUT and DATA IN indicate the port of the I/O device. FACET by Lab-Volt 305

2 Digital Logic Fundamentals The CS and R/W control signals are initiated by the CPU. The circuit shows how the CS and R/W control signals generate a WRITE or READ enable signal. The WRITE and READ signals are outputs to tri-state buffers that permit bidirectional data transfer between an I/O device and a CPU via a data bus. When the CS signal is low, both AND gates, labeled WRITE and READ, are disabled. As a result, the logic state of the R/W control signal has no effect on the output of the WRITE and READ gates; the WRITE and READ gate outputs are always low. 306 FACET by Lab-Volt

3 When the outputs of the WRITE and READ gates are low, the a. R/W control signal is low. b. CS control signal is low. A high CS signal enables both AND gates, labeled WRITE and READ. When the gates are enabled, the logic state of the R/W signal affects the outputs of the WRITE and READ gates. The inverter between the R/W signal and the WRITE gate ensures that the complement of the R/W signal is input to the WRITE gate. Consequently, the outputs of the WRITE and READ gates are always complementary when the CS signal is high. FACET by Lab-Volt 307

Digital Logic Fundamentals Can the outputs of the WRITE and READ gates be high at the same time? The output of the WRITE gate is high when the CS signal is high and R/W is low.

4 Digital Logic Fundamentals Can the outputs of the WRITE and READ gates be high at the same time? The output of the WRITE gate is high when the CS signal is high and R/W is low. The output of the READ gate is high when the CS signal is high and the R/W is high. The truth table for the READ and WRITE circuit is shown. A low CS control signal and a high R/W control signal cause the outputs of the WRITE gate to be a. high and the READ gate to be low. b. low and the READ gate to be high. c. low and the READ gate to be low. The circuit shows how the WRITE and READ signals from the AND gates control the tri-state buffers, WRITE and READ, to permit bidirectional data transfer between an I/O device and a CPU. 308 FACET by Lab-Volt

5 Line DB3 represents one of the data bus lines (bit 3). When the WRITE enable signal is high, the WRITE tri-state is enabled. Data can then be transferred from the CPU to the I/O device via the data bus. To transfer data from the CPU to an I/O device, which tri-state buffer has to be enabled? a. READ tri-state buffer b. WRITE tri-state buffer When the READ enabled signal is high, the READ tri-state is enabled. FACET by Lab-Volt 309

6 Digital Logic Fundamentals Data can then be transferred from the I/O device to the CPU via the data bus. When the READ tri-state buffer is enabled with a high READ signal, the output of the WRITE tri-state buffer is a. low. b. high. c. in a high impedance state. READ and WRITE tri-state buffers do not interact because only one buffer at a time is enabled. The high impedance (high-z) state of the disabled tri-state buffer disconnects the buffer from the circuit. When the CS control signal is low, the WRITE and READ signals are low, and the tri-state buffers are in high impedance states; the data bus and I/O port are effectively disconnected from the tri-state buffers. 310 FACET by Lab-Volt

7 What prevents a CPU from writing and reading data to an I/O device at the same time? a. The tri-state buffer outputs are always complementary. b. One or both of the tri-state buffers are always in a high impedance state. The DATA BUS CONTROL circuit block is shown. The label CPU BUS represents the data bus between the CPU and an I/O device. When the CPU is writing data to the I/O device, switch S1 sets the logic state of the CPU data bit: position H for high and position L for low. FACET by Lab-Volt 311

8 Digital Logic Fundamentals The labels DATA OUT and DATA IN respectively represent the connections to and from the data port of the I/O device. When the CPU is reading data from the I/O device, switch S2 sets the logic state of the data bit: position H for high and position L for low. PROCEDURE Locate the DATA BUS CONTROL and INPUT SIGNALS circuit blocks, and connect the circuit shown. Install a two-post connector in the BLOCK SELECT terminals at the left of the circuit block to activate the WRITE and READ AND gate LEDs. 312 FACET by Lab-Volt

9 Place INPUT SIGNALS toggle switches A and B in the LOW position. NOTE: Toggle switch A controls the logic state of the CS (chip select) signal. Toggle switch B controls the logic state of the R/W signal. You can determine the logic state of a signal by the LED status. When an LED is on (glowing), the signal logic state is high; when an LED is off (not glowing), the signal logic state is low. Effect of the CS and R/W Signals on the READ and WRITE Gates When the input signal A is set to LOW, the CS signal LED indicates that the CS signal is a. high. b. low. The R/W signal LED indicates that the R/W signal is a. high. b. low. FACET by Lab-Volt 313

10 Digital Logic Fundamentals With the CS control signal set to LOW, can the WRITE or READ gates be selected? With toggle switch B, change the logic state of the R/W signal to HIGH and then back to LOW while observing the output LEDs of the WRITE and READ gates. Did changing the logic state of R/W affect the logic state of the outputs of the WRITE or READ gates? The output states of the WRITE or READ gates did not change because a. the WRITE and READ gates are AND gates, which require two logic high inputs for a logic high output. b. of the inverter (NOT gate) between the R/W signal and the WRITE gate. 314 FACET by Lab-Volt

11 Set the CS signal to high by setting toggle switch A to HIGH. Toggle switch B should be set to LOW (R/W signal low). Is the WRITE gate or the READ gate selected (when high, the output LED glows)? a. WRITE b. READ Set the R/W signal high by setting toggle switch B to HIGH. Is the WRITE gate or READ gate selected? a. WRITE b. READ The purpose of the inverter between the R/W signal and the WRITE gate is to ensure that the a. outputs of the WRITE and READ gates are always complementary. b. output of the WRITE gate is low when the CS signal is high. FACET by Lab-Volt 315

12 Digital Logic Fundamentals For the WRITE gate output (CS WR signal) to be high, what must the logic states of the CS and R/W signals be? a. CS high and R/W low b. CS low and R/W low For the READ gate output (CS RD signal) to be high, what must the logic states of the CS and R/W signals be? a. CS high and R/W low b. CS high and R/W high Effect of the Read and Write Signals on Data Transfer Set the CS and R/W signals to low by setting toggle switches A and B to LOW. Install the twopost connector in the BLOCK SELECT terminals at the right of the circuit block to activate the LEDs at the WRITE and READ tri-state buffers. 316 FACET by Lab-Volt

13 Change the logic state of the data bit from the CPU to high, then low, high, and low by setting S1 to H, then L, H, and L. Does the WRITE tri-state buffer output LED indicate that the CPU is writing the data bit to the I/O device? Change the logic state of the data bit from the I/O device to high, then low, high, and low by setting S2 to H, then L, H, and L. Does the READ tri-state buffer LED indicate that the CPU is reading the data bit from the I/O device? The CPU cannot read or write data from or to the I/O device because the a. CS control signal is low. b. R/W control signal is low. c. data bits to and from the CPU cancel each other. FACET by Lab-Volt 317

14 Digital Logic Fundamentals Place the CPU in the write mode by setting the CS signal high (set toggle switch A to HIGH). The R/W signal is set low (toggle switch B at LOW). Change the logic state of the data bit from the CPU to high, then low, high, and low by setting S1 to H, then L, H, and L. Does the WRITE tri-state buffer LED indicate that the CPU is writing the data bit to the I/O device? Change the logic state of the data bit from the I/O device to high, then low, high, and low by setting S2 to H, then L, H, and L. Does the READ tri-state buffer LED indicate that the CPU is reading a data bit from the I/O device? 318 FACET by Lab-Volt

15 Place the CPU in the read mode by setting the R/W signal high (set toggle switch B to HIGH). Change the logic state of the data bit from the CPU to high, then low, high, and low by setting S1 to H, then L, H, and L. Does the WRITE tri-state buffer LED indicate that the CPU is writing the data bit to the I/O device? Change the logic state of the data bit from the I/O device to high, then low, high, and low by setting S2 to H, then L, H, and L. Does the READ tri-state buffer LED indicate that the CPU is reading a data bit from the I/O device when the CS is high and R/W is high? FACET by Lab-Volt 319

Digital Logic Fundamentals CONCLUSION A logic circuit within an I/O device controls bidirectional data transfer between the I/O device and the CPU via the data bus.

16 Digital Logic Fundamentals CONCLUSION A logic circuit within an I/O device controls bidirectional data transfer between the I/O device and the CPU via the data bus. The WRITE/READ data transfer logic circuit is composed of AND gates, tri-state buffers, and an inverter. Chip select (CS) and R/W control signals are inputs to the data transfer logic circuit of an I/O device. A high CS control signal selects a device for a write or read operation. A high R/W control signal causes the IC to read data from a memory or I/O device. A low R/W control signal causes the CPU to write data to a memory or I/O device. REVIEW QUESTIONS 1. Locate the DATA BUS CONTROL and INPUT SIGNALS circuit blocks and connect the circuit shown. Place CM switch 19 in the ON position to alter the circuit. Test the circuit with a voltmeter and by observing the LEDs while changing the logic states of the CS and R/W signals and the data switches, S1 and S2. A glowing LED indicates a high logic state. Which of the following statements is true? a. All circuit functions are normal. b. The WRITE tri-state buffer is always enabled. c. The WRITE tri-state is always disabled. d. The circuit cannot be selected. 2. When the data transfer is from the CPU to an I/O device, the CPU is a. simultaneously reading and writing data. b. transferring data bidirectionally. c. reading data. d. writing data. 320 FACET by Lab-Volt

17 3. When the data transfer is from an I/O device to the CPU, the CPU is a. simultaneously reading and writing data. b. transferring data bidirectionally. c. reading data. d. writing data. 4. The purpose of the chip select (CS) signal is to a. enable a CPU for a read or write operation. b. stop the CPU from reading or writing to the data bus. c. enable all memory devices in a computer. d. enable a memory or input/output device for a read or write operation. 5. If the R/W signal is high, a. data transfers from A to B. b. data transfers from B to A. c. both tri-states are enabled. d. both tri-states are disabled. NOTE: Make sure all CMs are cleared (turned off) before proceeding to the next section. FACET by Lab-Volt 321

Summer 2003 Lecture 21 07/15/03

Summer 2003 Lecture 21 07/15/03 Simple I/O Devices Simple i/o hardware generally refers to simple input or output ports. These devices generally accept external logic signals as input and allow the CPU