CSE/ESE 260M Introduction to Digital Logic and Computer Design. Lab 3 Supplement

Transcription

1 CSE/ESE 260M Introduction to Digital Logic and Computer Design Due 11/13/2013 and 11/20/2013 Lab 3 Supplement Recall and follow the General notes from lab 1. You may work in groups of up to 2 (but no more than 2) on this lab. You are required to hand in a paper lab report on 11/13/2013. The components of the lab report should be assembled in the order of the steps in the detailed instructions below, and the entire report must be securely fastened together, preferably with a single staple in the top left corner. The names of both group members should appear on the first page. 10 points will be deducted from labs that do not conform to these requirements. In this lab, we will be working with an FPGA development board manufactured by Opal Kelly, the XEM6002 ( The board has a Xilinx Spartan-6 FPGA, 4 push-buttons, 8 LEDs, a USB port for communicating with a computer, and 4 ports for attaching peripheral electronics (like thermometers, microphones, speakers, etc.). The FPGA is a reconfigurable logic circuit that can be used to implement arbitrary digital circuits. We could use it to do anything from making LEDs blink to creating a complete CPU. The board is powered by the USB connection, so to turn it on or off you plug it in or unplug it, respectively. Please follow these guidelines for both your own safety and the safety of the equipment around you: Never eat or drink in the lab! Keep the boards unplugged (i.e., powered down) when not in use. Don t directly touch the chips or pins on the board. Handle the boards by the edges. There is little danger of you being injured by an electric shock, but humans can build up very high voltages (on the order of 3 kv) before we feel anything. Electronics are easily damaged by much lower voltages, so be careful! (See and for more on the dangers of ESD.) - 1 -

2 In this lab, you will be building a multiplier circuit, multiplying two 7-bit values (m is the multiplicand, r is the multiplier) encoded in 2 s complement notation, resulting in a 14-bit product (called product). The multiplier circuit will perform its function over multiple clock cycles, utilizing Booth s multiplication algorithm (see the excellent description on the Wikipedia page below). Some of the elements of a data path are provided in the following figure: The inputs m and r are shown on the left, the output product is shown on the right, registers A, S, and P are in the center, and an ALU (similar to the one you designed in lab 2) is also provided. The ALU does not have any internal registers or memory elements (again, the same as the one from lab2). Its inputs are X and Y and its output is Z. The bit-widths of all inputs, outputs, registers, and ALU ins and outs are all as indicated in the data path figure. The ovals in the figure labeled wiring will need to include the appropriate routing and muxing necessary to complete the data path. To complete the lab, you must: (1) design and implement the ALU; (2) complete the design of the data path; and (3) design a controller that will enable the execution of Booth s multiplication algorithm. (1) Design an Arithmetic/Logic Unit (ALU) suitable for use as a component within the data path. As in lab 2, the ALU function will be controlled by a signal func (which can be as many bits as you wish). The ALU will have two 16-bit data inputs, labeled X and Y, and one 16-bit data output, labeled Z. The functions supported should include at least the following: func ALU function add Z = X + Y addition sub Z = X Y subtraction asr Z = asr X arithmetic shift right The arithmetic shift right is a right shift operation that replicates the previous most-significant bit as the new most-significant bit, in addition to shifting the top 15 bits right one bit-position. If you wish, you may expand the set of functions provided by the ALU, but your ALU must support at least the above three functions

3 (2) If you wish, you may add additional registers to the data path, or eliminate elements that you deem unnecessary. (3) Design a finite-state machine controller for your data path that implements Booth s algorithm. A reset input signal should initialize the data path registers to a reasonable value. On the clock cycle after removal of reset, the m and r inputs should be read, and over the subsequent clock cycles, the data path should execute Booth s algorithm and ultimately provide the product of m and r on the product output signal. Detailed instructions: 1. (20 points) Generate a VHDL description of the ALU described above in a file alu.vhd and a VHDL description of the multiplier circuit in a file booth.vhd, including appropriate header comments and other comments throughout. Include a printed copy of the files in your lab report. Also include a block diagram of your final data path (in the style of the figure above, with additional details provided) and documentation of your controller finite-state machine. The FSM documentation can be a state table, state diagram, or any other form that clearly indicates the details of the controller design. 2. (10 points) Generate a testbench file testbooth.vhd, so that you can use it to simulate your multiplier circuit. Include tests to verify several input values for m and r (including some negative values). Include a printed copy of the testbench in your lab report. 3. (10 points) Simulate the mulitiplier using your testbench. Set the radix of the data path signals to hexadecimal. Check the output carefully for errors and modify the design as necessary to ensure that it works correctly. Include a copy of the final simulation output in your lab report. Make sure that all signal values are clearly readable on the printed copy and that you select the print option that includes the signal names on every page of the printed output. Note that you may need to scale the printout to ensure that signal values are readable (do this, by specifying the number of pages of output to print). Add notes to the printed copy, identifying all places where each operation is performed. For each operation, verify that the result shown by the simulation is correct. If any result is not correct, make a note of it and explain why you were unable to correct the calculator source code. Items 1 to 3 above are due on 11/13/ (10 points) Deploy your multiplier circuit on the FPGA and test it out on the real hardware. Item 4 is due on 11/20/2013. Physical I/O on the board: Supplemental Information We will not be using the physical I/O on the board for this lab. If you wish, you can use the LED outputs for debugging purposes, using the techniques from lab 2 (recall that the LED signals are active low, a 0 turns the LED on and a 1 turns the LED off). Virtual I/O on the PC screen: In addition to the physical I/O on the board itself, we can deploy virtual inputs and outputs on the screen of the PC attached to the board s USB port. Logically, this is accomplished as indicated in the figure below

4 Software executes on the PC which presents a user interface. The functions supported by the user interface are described in an XML file which must be loaded into the FrontPanel software. For this lab, we will have two 7-bit inputs (representing m and r) that are provided in hexadecimal; one 14-bit output (representing product) that is presented in hexadecimal; and one 1-bit input (representing reset) that is presented by a pushbutton on the PC screen (labeled rst ). The virtual inputs and outputs are reproduced on the FPGA via the path illustrated in the figure, including the USB port on the PC, the USB controller on the Opal Kelly board, and the host interface and endpoints on the FPGA. In the terminology of the FrontPanel virtual interface, the host is the PC and the target device is the FPGA. The following internal signal definitions are used to interface the endpoints of the virtual interface with the user design: signal ep00wire : STD_LOGIC_VECTOR(15 downto 0); signal ep01wire : STD_LOGIC_VECTOR(15 downto 0); signal ep02wire : STD_LOGIC_VECTOR(15 downto 0); signal ep20wire : STD_LOGIC_VECTOR(15 downto 0); signal ep21wire : STD_LOGIC_VECTOR(15 downto 0); The first three are inputs to the user design (read ep01 as endpoint at address 01 hex ; addresses between 00 and 1F are inputs), and the latter two are outputs from the user design (addresses 20 to 3F are outputs). All are defined as 16-bits wide, we will use subsets of the full 16 bits to connect to the user design. Specifying the top-level design and synthesizing: Ensure that you have specified the right FPGA part and speed grade. See lecture slides from Sept. 16. Go to the class webpage to download lab3files.zip and extract the files to a folder on your H: drive. Each of the following files should be added to your project using Project -> Add copy of source : lab3top.vhd xem6002.ucf okcoreharness.ngc - 4 -

5 oklibrary.vhd okwirein.ngc okwireout.ngc TFIFO64x8a_64x8b.ngc In the previous lab, you needed to edit the file lab2top.vhd to instantiate your design. That is not required for this lab, as the lab3top.vhd already instantiates the Booth multiplier. If you wish to edit lab3top.vhd to utilize the LED outputs for debugging, use the techniques from the previous lab to do so. The file xem6002.ucf specifies the timing constraints and pin-out for the FPGA part. The remaining files specify the FPGA end of the virtual interface. You are now ready to synthesize your design. Synthesizing is very much like compiling for conventional computer languages, but instead of turning your code into instructions for a processor, it will turn your code into a network of components (e.g., logic gates and registers) connected by wires. Synthesize your design by selecting your top-level VHDL file in the Hierarchy panel and double clicking Synthesize XST in the Processes panel. (Note: the Implementation radio button above the Hierarchy panel must be lit, not the Simulation button.) It should run for a minute or two before reporting Process Synthesize XST completed successfully in the console. Your Design Summary page should update to report successful synthesis as well. Next double click on Generate Programming File in the Processes panel. This will take a minute or two, even for this simple design. The end result is a.bit file, also known as a programming or configuration file. Programming the FPGA: Once you have successfully generated a programming file for the FPGA, you can download it onto the development board using the Opal Kelly tools and the USB interface. Open the Opal Kelly FrontPanel application. It s listed in the start menu under All Programs > Opal Kelly > FrontPanelUSB on the lab computers. With no FPGA board connected, it should look like this: Plug your XEM6002 board into the computer using a USB Mini-B cable. A green LED labeled D9 should light indicating that it is powered and FrontPanel should detect the device: - 5 -

6 Click the FPGA icon to choose the programming (aka.bit or configuration ) file to download. Xilinx ISE will have placed the generated file in the root of your project directory. When you choose the file, FrontPanel will download the programming file onto the board. Click on the circle icon (to the left of the FPGA icon) to load a FrontPanel XML profile (provided as part of lab3files.zip). This will launch a new window with the virtual interface. Using the on-screen window to set the inputs, exercise your ALU to ensure that it operates as it should. Checkout logistics: The Bryan 316/306 lab spaces are available 9am to 4pm Monday through Friday. Stuart Cranor (his office is Bryan 308) can check out an Opal Kelly board to your group. Please return it by 4pm. Alternatively, during consulting hours, you can check out a board from the TAs. Please return it by the end of TA hours. When you are ready to demonstrate your functioning ALU, please show it to the instructor or a TA. Please make sure both lab partners are present for the demo