Schedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a

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1 ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser November 8, 2006 Midterm Average: 70 Lecture 16: Midterm Solutions Homework 6: Calculator Handshaking HW 6: Due Wednesday, November 15 Project Progress reports due Friday, Nov 10 Schedule Homework 6 due Wednesday, November 15 Complete the Calculator from ECEU323 in VHDL Write a controller Combine controller and datapath Use the posted entities Project progress report due Friday, November 10: and to me telling me where your project stands some working VHDL code in your home directory November 15 th and 20 th : student presentations on projects: sign up for a date to do your project presentation Sign up to demo your working project code to me November 20 th or 21 st ECE U530 F06 2 Rest of Semester Lecture Monday November 13: Using memories in VHDL Upcoming lectures: Designing a complex multiply accumulator: Chapter 6 of Ashenden Midterm Question 1a Give an example of a case statement where you need an others clause and an example where you do not. You can either explain in words, or show VHDL code. Quiz in class on December 4 Project due dates: Nov 20: Preliminary Project Report Dec 13: Final Project Report Due 3 4

2 Midterm 1b The following snippet of VHDL code is incorrect. Explain what is wrong and correct the problem: signal A,B: std_logic_vector(5 downto 0); signal F: std_logic_vector(6 downto 0); F <= A + B; Midterm 1c A designer, who wanted to implement some combinational logic for an and-or-invert gate whose output is stored in a flipflop, wrote the following code: process(clk) if rising_edge(clk) then E <= A and B; F <= C and D; G <= E or F; Q<= not(g); end if; end process; Is this code correct? If yes, explain why. If not, fix it. 5 6 Midterm 1d Midterm 1e What are 2 VHDL constructs that will synthesize latches when you do not want them? Why are the latches synthesized? For combinational circuitry, when should you use the VHDL if then else construct and when should you avoid it? 7 8

3 Midterm Question 2 Write VHDL code for a 6-bit 3-to-1 multiplexer. entity threemux is Port ( S : in std_logic_vector(1 downto 0); A, B, C: in std_logic_vector(5 downto 0); Y : out std_logic_vector(5 downto 0)); end threemux; architecture Behavioral of threemux is process(s, A, B, C) case S is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when others => Y <= "------"; end case;end process; end Behavioral; Midterm Q3 Below is correct VHDL code for a shift register: library ieee; use ieee.std_logic_1164.all; entity shift is port(clk, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(3 downto 0); process wait until (Clk'event and Clk = '1'); tmp <= tmp(2 downto 0) & SI; end process; SO <= tmp(3); end archi; (a) Identify the line or lines of code that will cause flipflops to be inferred Midterm Q3b Midterm Q3c Draw the schematic that will be synthesized from this code. Your schematic should consist of flipflops and any additional logic gates needed. (c) Rewrite the code to include an asynchronous, active high reset. entity shift is port(clk, SI, Reset : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(3 downto 0); process (reset, clk) if reset = '1' then tmp <= "0000"; elsif (Clk'event and Clk = '1') then tmp <= tmp(2 downto 0) & SI; end if; end process; SO <= tmp(3); end archi; 11 12

4 Midterm Q4 A circular shift register or ring counter connects the output of a shift register to its input. The counter is triggered on the rising edge of the clock. Your counter should count (shift left) on every clock edge. It should be reset to 0001 on an active high reset signal. (a) (4 pts) Fill in the table to indicate the expected behavior of your ring counter. Reset Clk Count Midterm Q4b Write VHDL code for a 4-bit ring counter with active high reset. entity ring is port(clk, Reset : in std_logic; Count : out std_logic_vector(3 downto 0)); end ring; architecture Behavioral of ring is signal temp: std_logic_vector(3 downto 0); process (Clk, Reset) if reset = '1' then temp <= "0001"; elsif rising_edge(clk) then temp <= temp(2 downto 0) & temp(3); end if; end process; count <= temp; end Behavioral; Midterm Q5: code Midterm Q5 architecture with_fn of fsm is type state_type is (A, B, C); signal present, nxt:state_type; process (CLK, RESET) if RESET='1' then present <= A; elsif (CLK'event and CLK='1') then present <=nxt; end if; end process; PROCESS (present, x) BEGIN CASE present IS WHEN a => IF x = '1' THEN nxt <= a; ELSE nxt <= b; END IF; Z <= '0'; WHEN b => IF x = '0' THEN nxt <= b; ELSE nxt <= c; END IF; Z <= '0'; WHEN c => IF x = '0' THEN nxt <= b; Z <= '1'; ELSE nxt <=a; Z <= '0'; END IF; END CASE; END PROCESS; end architecture; (a) (8 pts) Draw the state machine described by this code. (b) (4pts) What function does this state machine implement? Be specific

5 Midterm Q5c Calculator: Lab 5 When this VHDL code is synthesized, the Xilinx tools recognize a state machine and synthesize the logic needed. Part of this task is state assignment. What is assigned when the tools do state assignment? How is the state assignment determined? Calculator Entity library IEEE; use IEEE.std_logic_1164.all; entity Calc is port (sw: in STD_LOGIC_VECTOR(7 downto 0); -- instruction and data input bus reset: in STD_LOGIC; -- active high reset signal exc: in STD_LOGIC; -- execution signal, active high clk: in STD_LOGIC; -- clock signal dout: out STD_LOGIC_VECTOR (3 downto 0); -- data output cout: out STD_LOGIC -- 4th bit from tos, -- indicates error flag ); end Calc; 19 Calculator Architecture architecture Calc_arch of Calc is component ctrl port (reset: in STD_LOGIC; -- active high reset signal clk : in STD_LOGIC; -- clock signal exc : in STD_LOGIC; -- execution signal active high sw : in STD_LOGIC_VECTOR(7 downto 4); -- instruction sm : out STD_LOGIC; -- mux select signal sa : out std_logic_vector (2 downto 0); -- alu select ss : out std_logic_vector (1 downto 0)); -- stack select end component; component datapath port (reset : in STD_LOGIC; -- asynchronous reset din : in std_logic_vector (3 downto 0); -- input data dout: out std_logic_vector (3 downto 0); -- output data cout : out std_logic; -- carry, borrow or overlow flag sm : in std_logic; -- mux selector sa ss : in std_logic_vector (2 downto 0); -- alu select : in std_logic_vector (1 downto 0); -- stack select clk : in std_logic ); -- clock end component; -- <<enter your statements here>> end Calc_arch; 20

6 Controller Entity library IEEE; use IEEE.std_logic_1164.all; entity ctrl is port ( reset: in STD_LOGIC; -- active high reset signal clk : in STD_LOGIC; -- clock signal exc : in STD_LOGIC; -- execution signal, active high sw : in STD_LOGIC_VECTOR (7 downto 4); -- instruction input sm: out STD_LOGIC; -- mux select signal sa: out std_logic_vector (2 downto 0); -- alu select ss: out std_logic_vector (1 downto 0) ); -- stack select ); end ctrl; architecture ctrl_arch of ctrl is -- <<enter your statements here>> end ctrl_arch; Controller for Calculator Always go through all the states EXE = 0 Reset Wait EXE = 1 TOS1 TOS2 PUSH Controller for Calculator Push instruction TOS1: hold stack TOS2: hold stack, put input in temp register PUSH: push input Pop instruction TOS1: pop TOS2: hold stack TOS3: hold stack Add TOS1 + TOS2 TOS1: Put TOS in temp register, pop stack TOS2: Add TOS to temp register, pop stack PUSH: Push result Handshaking Handshaking is important for interfacing to designs How do you know when your inputs have data? How do you signal that your results are ready? Handshaking is useful for testbenches: Allows you to use the same testbench even if internal timing of your hardware changes

7 Handshaking En -- an input signal telling the hardware to start Valid -- an output signal saying the result is ready What is wrong with this model? Sender En Valid inputs Hardware Handshaking One signal for input: Enable One signal for output: Valid How do you know if HW is ready? How do you know that HW has read the input data? How does HW know that Sender has read the output? result Signaling Protocol Signaling Protocol: communication protocol req: initiate an action ack: signal completion of that action Two handshake signals for send data Control Signaling Protocol Four-phase Handshaking protocol Sender req data ack Receiver Level signaling or return to zero Sender Receiver req ack data 27 28

8 Control Signaling Protocol Two-phase Handshaking protocol Importance of Handshaking Hardware needs to know when inputs are ready Software needs to know when results are valid Different designs can have different timing Behavioral Register Transfer Level (RTL) Pipelined version vs. non-pipelined version Transition signaling or Non-return to zero req Sender data 29 ack Receiver Can use the same testbench with different hardware timing if you use handshaking in your hardware design 30