th International Design & Test Symposium (IDT 2015)
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1 th International Design & Test Symposium (IDT 2015) Dead Sea, Amman, Jordan December 2015 IEEE Catalog Number: ISBN: CFP1563D-POD
2 Copyright 2015 by the Institute of Electrical and Electronic Engineers, Inc All Rights Reserved Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ All rights reserved. ***This publication is a representation of what appears in the IEEE Digital Libraries. Some format issues inherent in the e-media version may also appear in this print version. IEEE Catalog Number: CFP1563D-POD ISBN (Print-On-Demand): ISBN (Online): ISSN: Additional Copies of This Publication Are Available From: Curran Associates, Inc 57 Morehouse Lane Red Hook, NY USA Phone: (845) Fax: (845) curran@proceedings.com Web:
3 Table of Contents Organizing Committee Program Committee Keynote addresses Keynote 1: M erger M ania Keynote 2: Electronics and Computing: Past, Present, and Future Said Hamdioui Keynote 3: Ensuring Robustness in Today's IoT Era... Invited Talks Special Session 1: HW Security and Reliability Transforming Between Logic Locking and IC Camouflaging... 1 Muhammad Yasin and Ozgur Sinanoglu Obfuscated Arbitrary Computation using Cryptographic Primitives Nektarios Georgios Tsoutsos and Michail Maniatakos Reliability Degradation in the Scope of Aging From Physical to System Level... 9 Hussam Amrouch and Jörg Henkel Special Session 2: Validation and Verification Revolutionizing Validation: The Intel Approach for TTM Raed ElOmari and Shahil Rais SoC Verification Platforms Using HW Emulation and Co-modeling Testbench Technologies Mohamed AbdElSalam and Ashraf Salem Regular papers: Session 1:Multi-Core Architectures Chip-Level Programming of Heterogeneous Multiprocessors Mwaffaq Otoom and Joann Paul Heterogeneous Multi-Core Architecture for a 4G Communication in High-Speed Railway.. 26 Mariem Makni, Mouna Baklouti, Smail Niar, Morteza Biglari-Abhari and Mohamed Abid Memory Profiling for Intra-Application Data-Communication Quantification: A Survey Imran Ashraf, Mottaqiallah Taouil and Koen Bertels
4 Session 2: Analog Design A 10 Gbps ADC-Based Equalizer for Serial I/O Receiver Ahmed Elhady, Khaled El-Gammal and Sameh Ibrahim A Low-Temperature-Coefficient Curvature-Compensated Bandgap Reference with Mismatch Attenuation Mahitab F. Eladwy, Sameh A. Ibrahim and Mohamed Dessouky Session 3: Simulation and Verification Toward the Interfacing of SystemC-AMS Models with Hardware-Emulated Platforms Hanan Tawfik, Mona Safar, Mohamed Abdelsalam, M. Watheq El-Kharashi and Ashraf Salem Guiding Intelligent Testbench Automation Using Data Mining and Formal Methods Eman El Mandouh and Amr G. Wassal Session 4: Hardware Testing Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams Raimund Ubar, Mario Schölzel, Stephen Adeboye Oyeniran and Heinrich T. Vierhaus Reconfigurable Test Platform for Modular Embedded Systems in Manufacturing Processes 72 Silviu Folea, Szilárd Enyedi, Liviu Miclea and Horia Hedeiu An Automatic ECG Generator for Testing and Evaluating ECG Sensor Algorithms Hussam Al Hamadi, Amjad Gawanmeh and Mahmoud Al-Qutayri Session 5: Data Management and Design Space Exploration Efficient Data Management on 3D Stacked Memory for Big Data Applications Cheng Qian, Libo Huang, Peng Xie, Nong Xiao and Zhiying Wang A Bi-Objective Heuristic for Heterogeneous MPSoC Design Space Exploration Lotfi Braham Mediouni, Smail Niar, Rachid Benmansour, Karima Benatchba and Mouloud Koudil NRTBox: A Matlab Simulink Toolbox for NoC Switch Performance Evaluation and Early Architectural Exploration Using Discrete Event Simulation Samir Ben Abid, Nejib Mediouni, Oussama Kallel and Salem Hasnaoui Session 6: Reliability and Test BTI Analysis of SRAM Write Driver Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans and Francky Catthoor Aging and Leakage Tradeoff in VLSI Circuits Hao Luo and Mehrdad Nourani Testing of 3D IC with minimum power using Genetic Algorithm Tanusree Kaibartta and Debesh Das
5 Session 7: Built-in Self-Test A Method of LFSR Seed Generation for Hierarchical BIST Kosuke Sawaki and Satoshi Ohtake SR-TPG: A Low Transition Test Pattern Generator for Test-per-Clock and Test-per-Scan BIST Abdallatif Abu-Issa, Iyad Tumar and Wasel Ghanem Session 8: Hardware Security Facilitating Side Channel Analysis by Obfuscation for Hardware Trojan Detection Arash Nejat, David Hely and Vincent Beroulle FPGA Implementation of Scalar Multiplication over Fp for Elliptic Curve Cryptosystem. 135 Ahmed Bellemou, Mohamed Anane, Nadjia Benblidia and Mohamed Issad Posters Session A Novel Wavelet-Based Method for TSV Modeling Khaled Mohamed High level NoC Modeling Using Discrete Event Simulation Nejib Mediouni, Samir Ben Abid, Oussama Kallel and Salem Hasnaoui A proposed methodology to improve UVM-Based test generation and coverage closure Khaled Mohamed, Khaled Kabil and Rafik Guindi Automatic Test Pattern Generation for Virtual Hardware Model using Constrained Symbolic Execution Nahla El Nemr, Mona Safar, Ayman Wahba and Ashraf Salem SimEvents Based High Level Early Design Space Exploration and Modeling of a 3D Network onchip Nejib Mediouni, Samir Ben Abid, Oussama Kallel and Salem Hasnaoui Design Constraints and Challenges behind Fault Tolerance System in a MobileApplicationFramework Venkata Narasimha Inukollu, Taeghyun Kang and Nina Sakhnini
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